2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
6 #include <cpu/x86/lapic.h>
9 #include "option_table.h"
10 #include "pc80/mc146818rtc_early.c"
11 #include "pc80/serial.c"
12 #include "console/console.c"
13 #include "lib/ramtest.c"
14 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
15 #include "northbridge/intel/e7501/raminit.h"
16 #include "cpu/x86/lapic/boot_cpu.c"
17 #include "northbridge/intel/e7501/debug.c"
18 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
19 #include "cpu/x86/mtrr/earlymtrr.c"
20 #include "cpu/x86/bist.h"
22 #define SUPERIO_PORT 0x2e
23 #define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
25 static void hard_reset(void)
30 static inline int spd_read_byte(unsigned device, unsigned address)
32 return smbus_read_byte(device, address);
35 #include "northbridge/intel/e7501/raminit.c"
36 #include "northbridge/intel/e7501/reset_test.c"
37 #include "lib/generic_sdram.c"
39 // This function MUST appear last (ROMCC limitation)
40 static void main(unsigned long bist)
42 static const struct mem_controller memctrl[] = {
44 .d0 = PCI_DEV(0, 0, 0),
45 .d0f1 = PCI_DEV(0, 0, 1),
46 .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
47 .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
53 // Skip this if there was a built in self test failure
58 // Get the serial port running and print a welcome banner
60 lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
64 // Halt if there was a built in self test failure
65 report_bist_failure(bist);
67 // print_pci_devices();
69 // If this is a warm boot, some initialization can be skipped
71 if (!bios_reset_detected())
74 // dump_spd_registers(&memctrl[0]);
75 // dump_smbus_registers();
76 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
79 // NOTE: ROMCC dies with an internal compiler error
80 // if the following line is removed.
81 print_debug("SDRAM is up.\n");