src/mainboard/intel/xe7501devkit/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include <stdlib.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "southbridge/intel/i82801ca/i82801ca_early_smbus.c"
  17 #include "northbridge/intel/e7501/raminit.h"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/intel/e7501/debug.c"
  20 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
  21 #include "cpu/x86/mtrr/earlymtrr.c"
  22 #include "cpu/x86/bist.h"
  23
  24 #define SUPERIO_PORT    0x2e
  25 #define SERIAL_DEV              PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
  26
  27 static void hard_reset(void)
  28 {
  29         outb(0x0e, 0x0cf9);
  30 }
  31
  32 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  33 {
  34         /* nothing to do */
  35 }
  36
  37 static inline int spd_read_byte(unsigned device, unsigned address)
  38 {
  39         return smbus_read_byte(device, address);
  40 }
  41
  42 #include "northbridge/intel/e7501/raminit.c"
  43 #include "northbridge/intel/e7501/reset_test.c"
  44 #include "sdram/generic_sdram.c"
  45
  46
  47 // This function MUST appear last (ROMCC limitation)
  48 static void main(unsigned long bist)
  49 {
  50         static const struct mem_controller memctrl[] = {
  51                 {
  52                         .d0 = PCI_DEV(0, 0, 0),
  53                         .d0f1 = PCI_DEV(0, 0, 1),
  54                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  55                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
  56                 },
  57         };
  58
  59         if (bist == 0)
  60         {
  61                 // Skip this if there was a built in self test failure
  62
  63                 early_mtrr_init();
  64         enable_lapic();
  65     }
  66
  67         // Get the serial port running and print a welcome banner
  68
  69     lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  70     uart_init();
  71     console_init();
  72
  73     // Halt if there was a built in self test failure
  74         report_bist_failure(bist);
  75
  76 //      print_pci_devices();
  77
  78         // If this is a warm boot, some initialization can be skipped
  79
  80         if (!bios_reset_detected())
  81         {
  82                 enable_smbus();
  83 //      dump_spd_registers(&memctrl[0]);
  84 //      dump_smbus_registers();
  85
  86 //              memreset_setup();               No-op for this chipset
  87                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
  88         }
  89
  90         // NOTE: ROMCC dies with an internal compiler error
  91         //               if the following line is removed.
  92         print_debug("SDRAM is up.\r\n");
  93 }