src/mainboard/intel/xe7501devkit/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 arch i386 end
   6
   7 ##
   8 ## Build the objects we have code for in this directory.
   9 ##
  10
  11 driver mainboard.o
  12 if CONFIG_HAVE_MP_TABLE                 object mptable.o         end
  13 if CONFIG_HAVE_PIRQ_TABLE               object irq_tables.o      end
  14 if CONFIG_HAVE_ACPI_TABLES      object acpi_tables.o end
  15 object reset.o
  16
  17 ##
  18 ## Romcc output
  19 ##
  20 makerule ./failover.E
  21         depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
  22         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
  23 end
  24
  25 makerule ./failover.inc
  26         depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
  27         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
  28 end
  29
  30 makerule ./auto.E
  31         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  32         action  "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  33 end
  34 makerule ./auto.inc
  35         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  36         action  "../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  37 end
  38
  39 ##
  40 ## Build our 16 bit and 32 bit coreboot entry code
  41 ##
  42 mainboardinit cpu/x86/16bit/entry16.inc
  43 mainboardinit cpu/x86/32bit/entry32.inc
  44 ldscript /cpu/x86/16bit/entry16.lds
  45 ldscript /cpu/x86/32bit/entry32.lds
  46
  47 ##
  48 ## Build our reset vector (This is where coreboot is entered)
  49 ##
  50 if CONFIG_HAVE_FALLBACK_BOOT
  51     if CONFIG_USE_FALLBACK_IMAGE
  52             mainboardinit cpu/x86/16bit/reset16.inc
  53             ldscript /cpu/x86/16bit/reset16.lds
  54     else
  55             mainboardinit cpu/x86/32bit/reset32.inc
  56             ldscript /cpu/x86/32bit/reset32.lds
  57     end
  58 else
  59         mainboardinit cpu/x86/16bit/reset16.inc
  60         ldscript /cpu/x86/16bit/reset16.lds
  61 end
  62
  63 ### Should this be in the northbridge code?
  64 mainboardinit arch/i386/lib/cpu_reset.inc
  65
  66 ##
  67 ## Include an id string (For safe flashing)
  68 ##
  69 mainboardinit arch/i386/lib/id.inc
  70 ldscript /arch/i386/lib/id.lds
  71
  72 ###
  73 ### This is the early phase of coreboot startup
  74 ### Things are delicate and we test to see if we should
  75 ### failover to another image.
  76 ###
  77 if CONFIG_USE_FALLBACK_IMAGE
  78         ldscript /arch/i386/lib/failover.lds
  79         mainboardinit ./failover.inc
  80 end
  81
  82 ###
  83 ### O.k. We aren't just an intermediary anymore!
  84 ###
  85
  86 ##
  87 ## Setup RAM
  88 ##
  89 mainboardinit cpu/x86/fpu/enable_fpu.inc
  90 mainboardinit cpu/x86/mmx/enable_mmx.inc
  91 mainboardinit cpu/x86/sse/enable_sse.inc
  92 mainboardinit ./auto.inc
  93 mainboardinit cpu/x86/sse/disable_sse.inc
  94 mainboardinit cpu/x86/mmx/disable_mmx.inc
  95
  96 ##
  97 ## Include the secondary Configuration files
  98 ##
  99 dir /pc80
 100
 101 config chip.h
 102
 103 # based on sample config for tyan/s2735
 104 chip northbridge/intel/e7501
 105         device pci_domain 0 on
 106                 device pci 0.0 on end # Chipset host controller
 107                 device pci 0.1 on end # Host RASUM controller
 108                 device pci 2.0 on # Hub interface B
 109                         chip southbridge/intel/i82870 # P64H2
 110                                 device pci 1c.0 on end # IOAPIC - bus B
 111                                 device pci 1d.0 on end # Hub to PCI-B bridge
 112                                 device pci 1e.0 on end # IOAPIC - bus A
 113                                 device pci 1f.0 on end # Hub to PCI-A bridge
 114                         end
 115                 end
 116                 device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
 117                 device pci 4.0 on # Hub interface D
 118                         chip southbridge/intel/i82870 # P64H2
 119                                 device pci 1c.0 on end # IOAPIC - bus B
 120                                 device pci 1d.0 on end # Hub to PCI-B bridge
 121                                 device pci 1e.0 on end # IOAPIC - bus A
 122                                 device pci 1f.0 on end # Hub to PCI-A bridge
 123                         end
 124                 end
 125                 device pci 6.0 on end # E7501 Power management registers? (undocumented)
 126                 chip southbridge/intel/i82801ca
 127                         device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
 128                         device pci 1d.1 off end # USB (not populated)
 129                         device pci 1d.2 off end # USB (not populated)
 130                         device pci 1e.0 on # Hub to PCI bridge
 131                                 chip drivers/pci/onboard # VGA ROM
 132                                         device pci 0.0 on end
 133                                 end
 134                         end
 135                         device pci 1f.0 on # LPC bridge
 136                                 chip superio/smsc/lpc47b272
 137                                         device pnp 2e.0 off # Floppy
 138                                                 io 0x60 = 0x3f0
 139                                                 irq 0x70 = 6
 140                                                 drq 0x74 = 2
 141                                         end
 142                                         device pnp 2e.3 off # Parallel Port
 143                                                 io 0x60 = 0x378
 144                                                 irq 0x70 = 7
 145                                         end
 146                                         device pnp 2e.4 on # Com1
 147                                                 io 0x60 = 0x3f8
 148                                                 irq 0x70 = 4
 149                                         end
 150                                         device pnp 2e.5 off # Com2
 151                                                 io 0x60 = 0x2f8
 152                                                 irq 0x70 = 3
 153                                         end
 154                                         device pnp 2e.7 on # Keyboard
 155                                                 io 0x60 = 0x60
 156                                                 io 0x62 = 0x64
 157                                                 irq 0x70 = 1 # Keyboard interrupt
 158                                                 irq 0x72 = 12 # Mouse interrupt
 159                                         end
 160                                         device pnp 2e.a off end # ACPI
 161                                 end
 162                         end
 163                         device pci 1f.1 on end # IDE
 164                         device pci 1f.3 on end # SMBus
 165                         device pci 1f.5 off end # AC97 Audio
 166                         device pci 1f.6 off end # AC97 Modem
 167                 end # SB
 168         end # PCI_DOMAIN
 169         device apic_cluster 0 on
 170                 chip cpu/intel/socket_mPGA604
 171                         device apic 0 on end
 172                 end
 173                 chip cpu/intel/socket_mPGA604
 174                         device apic 6 on end
 175                 end
 176         end
 177 end