1 ##################################################################
2 ## BEGIN BOILERPLATE - DO NOT EDIT
4 ## Compute the location and size of where this firmware image
5 ## (coreboot plus payload) will live in the boot rom chip.
8 # The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
10 default ROM_SECTION_SIZE = FALLBACK_SIZE
11 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
14 # The normal image goes at the beginning of the coreboot ROM region
15 # and uses all the remaining space
17 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
18 default ROM_SECTION_OFFSET = 0
22 ## Compute where this copy of coreboot will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up coreboot,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE = 65536
33 default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
36 ##################################################################
41 ## Build the objects we have code for in this directory.
45 if HAVE_MP_TABLE object mptable.o end
46 if HAVE_PIRQ_TABLE object irq_tables.o end
47 if HAVE_ACPI_TABLES object acpi_tables.o end
50 # Include the VGA option ROM, but only if we're compiled to use it
65 depends "$(MAINBOARD)/failover.c ../romcc"
66 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
69 makerule ./failover.inc
70 depends "$(MAINBOARD)/failover.c ../romcc"
71 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
75 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
76 action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
79 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
80 action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
84 ## Build our 16 bit and 32 bit coreboot entry code
86 mainboardinit cpu/x86/16bit/entry16.inc
87 mainboardinit cpu/x86/32bit/entry32.inc
88 ldscript /cpu/x86/16bit/entry16.lds
89 ldscript /cpu/x86/32bit/entry32.lds
92 ## Build our reset vector (This is where coreboot is entered)
96 mainboardinit cpu/x86/16bit/reset16.inc
97 ldscript /cpu/x86/16bit/reset16.lds
99 mainboardinit cpu/x86/32bit/reset32.inc
100 ldscript /cpu/x86/32bit/reset32.lds
103 mainboardinit cpu/x86/16bit/reset16.inc
104 ldscript /cpu/x86/16bit/reset16.lds
107 ### Should this be in the northbridge code?
108 mainboardinit arch/i386/lib/cpu_reset.inc
111 ## Include an id string (For safe flashing)
113 mainboardinit arch/i386/lib/id.inc
114 ldscript /arch/i386/lib/id.lds
117 ### This is the early phase of coreboot startup
118 ### Things are delicate and we test to see if we should
119 ### failover to another image.
121 if USE_FALLBACK_IMAGE
122 ldscript /arch/i386/lib/failover.lds
123 mainboardinit ./failover.inc
127 ### O.k. We aren't just an intermediary anymore!
133 mainboardinit cpu/x86/fpu/enable_fpu.inc
134 mainboardinit cpu/x86/mmx/enable_mmx.inc
135 mainboardinit cpu/x86/sse/enable_sse.inc
136 mainboardinit ./auto.inc
137 mainboardinit cpu/x86/sse/disable_sse.inc
138 mainboardinit cpu/x86/mmx/disable_mmx.inc
141 ## Include the secondary Configuration files
147 # based on sample config for tyan/s2735
148 chip northbridge/intel/e7501
149 device pci_domain 0 on
150 device pci 0.0 on end # Chipset host controller
151 device pci 0.1 on end # Host RASUM controller
152 device pci 2.0 on # Hub interface B
153 chip southbridge/intel/i82870 # P64H2
154 device pci 1c.0 on end # IOAPIC - bus B
155 device pci 1d.0 on end # Hub to PCI-B bridge
156 device pci 1e.0 on end # IOAPIC - bus A
157 device pci 1f.0 on end # Hub to PCI-A bridge
160 device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
161 device pci 4.0 on # Hub interface D
162 chip southbridge/intel/i82870 # P64H2
163 device pci 1c.0 on end # IOAPIC - bus B
164 device pci 1d.0 on end # Hub to PCI-B bridge
165 device pci 1e.0 on end # IOAPIC - bus A
166 device pci 1f.0 on end # Hub to PCI-A bridge
169 device pci 6.0 on end # E7501 Power management registers? (undocumented)
170 chip southbridge/intel/i82801ca
171 device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
172 device pci 1d.1 off end # USB (not populated)
173 device pci 1d.2 off end # USB (not populated)
174 device pci 1e.0 on # Hub to PCI bridge
175 chip drivers/pci/onboard # VGA ROM
176 device pci 0.0 on end
177 register "rom_address" = "_vgarom_start"
180 device pci 1f.0 on # LPC bridge
181 chip superio/smsc/lpc47b272
182 device pnp 2e.0 off # Floppy
187 device pnp 2e.3 off # Parallel Port
191 device pnp 2e.4 on # Com1
195 device pnp 2e.5 off # Com2
199 device pnp 2e.7 on # Keyboard
202 irq 0x70 = 1 # Keyboard interrupt
203 irq 0x72 = 12 # Mouse interrupt
205 device pnp 2e.a off end # ACPI
208 device pci 1f.1 on end # IDE
209 device pci 1f.3 on end # SMBus
210 device pci 1f.5 off end # AC97 Audio
211 device pci 1f.6 off end # AC97 Modem
214 device apic_cluster 0 on
215 chip cpu/intel/socket_mPGA604
218 chip cpu/intel/socket_mPGA604