2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
27 static void *smp_write_config_table(void *v)
29 static const char sig[4] = "PCMP";
30 static const char oem[8] = "Intel ";
31 static const char productid[12] = "Truxton ";
32 struct mp_config_table *mc;
40 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
41 memset(mc, 0, sizeof(*mc));
43 memcpy(mc->mpc_signature, sig, sizeof(sig));
44 mc->mpc_length = sizeof(*mc); /* initially just the header */
46 mc->mpc_checksum = 0; /* not yet computed */
47 memcpy(mc->mpc_oem, oem, sizeof(oem));
48 memcpy(mc->mpc_productid, productid, sizeof(productid));
51 mc->mpc_entry_count = 0; /* No entries yet... */
52 mc->mpc_lapic = LAPIC_ADDR;
57 smp_write_processors(mc);
61 dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
63 bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
64 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
68 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
73 dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
75 bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
78 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
82 dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
84 bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
87 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
91 /* define bus and isa numbers */
92 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
93 smp_write_bus(mc, bus_num, "PCI ");
95 smp_write_bus(mc, bus_isa, "ISA ");
98 smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000);
100 /* ISA backward compatibility interrupts */
101 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
102 bus_isa, 0x00, 0x8, 0x00);
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
104 bus_isa, 0x01, 0x8, 0x01);
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
106 bus_isa, 0x00, 0x8, 0x02);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
108 bus_isa, 0x03, 0x8, 0x03);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
110 bus_isa, 0x04, 0x8, 0x04);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
112 bus_isa, 0x06, 0x8, 0x06);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
114 bus_isa, 0x08, 0x8, 0x08);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
116 bus_isa, 0x09, 0x8, 0x09);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
118 bus_isa, 0x0c, 0x8, 0x0c);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
120 bus_isa, 0x0d, 0x8, 0x0d);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
122 bus_isa, 0x0e, 0x8, 0x0e);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_isa, 0x0f, 0x8, 0x0f);
126 /* Standard local interrupt assignments */
127 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
128 bus_isa, 0x00, MP_APIC_ALL, 0x00);
129 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
130 bus_isa, 0x00, MP_APIC_ALL, 0x01);
132 /* IMCH/IICH PCI devices */
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
134 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
136 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
138 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
140 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
142 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
144 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
149 bus_pea0, (0<<2)|0, 0x8, 0x10);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
151 bus_pea0, (0<<2)|1, 0x8, 0x11);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
153 bus_pea0, (0<<2)|2, 0x8, 0x12);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
155 bus_pea0, (0<<2)|3, 0x8, 0x13);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
161 bus_pea1, (0<<2)|0, 0x8, 0x10);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
163 bus_pea1, (0<<2)|1, 0x8, 0x11);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
165 bus_pea1, (0<<2)|2, 0x8, 0x12);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
167 bus_pea1, (0<<2)|3, 0x8, 0x13);
171 /* AIOC PCI devices */
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
173 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
175 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
177 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
180 /* There is no extension information... */
182 /* Compute the checksums */
183 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
185 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
186 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
187 mc, smp_next_mpe_entry(mc));
188 return smp_next_mpe_entry(mc);
191 unsigned long write_smp_table(unsigned long addr)
194 v = smp_write_floating_table(addr);
195 return (unsigned long)smp_write_config_table(v);