2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Arastra, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License version 2 as
8 ## published by the Free Software Foundation.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 uses USE_FALLBACK_IMAGE
25 uses HAVE_FALLBACK_BOOT
28 uses CONFIG_LOGICAL_CPUS
37 uses ROM_SECTION_OFFSET
38 uses CONFIG_ROM_PAYLOAD
39 uses CONFIG_ROM_PAYLOAD_START
40 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
47 uses LB_CKS_RANGE_START
51 uses MAINBOARD_PART_NUMBER
53 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
54 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
55 uses COREBOOT_EXTRA_VERSION
56 uses CONFIG_UDELAY_TSC
57 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
60 uses CONFIG_CONSOLE_SERIAL8250
64 uses DEFAULT_CONSOLE_LOGLEVEL
65 uses MAXIMUM_CONSOLE_LOGLEVEL
66 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
78 ## ROM_SIZE is the size of boot ROM that this board will use.
80 default ROM_SIZE = 2 * 1024 * 1024
83 ## Build code for the fallback boot
85 default HAVE_FALLBACK_BOOT=1
88 ## Delay timer options
91 default CONFIG_UDELAY_TSC=1
92 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
95 ## Build code to reset the motherboard from coreboot
97 default HAVE_HARD_RESET=1
100 ## Build code to export a programmable irq routing table
102 default HAVE_PIRQ_TABLE=1
103 default IRQ_SLOT_COUNT=1
106 ## Build code to export an x86 MP table
107 ## Useful for specifying IRQ routing values
109 default HAVE_MP_TABLE=1
112 ## Build code for SMP support
113 ## Only worry about 2 micro processors
116 default CONFIG_MAX_CPUS=4
117 default CONFIG_LOGICAL_CPUS=0
120 ## Build code to setup a generic IOAPIC
122 default CONFIG_IOAPIC=1
125 ## Clean up the motherboard id strings
127 default MAINBOARD_PART_NUMBER="Truxton"
128 default MAINBOARD_VENDOR= "Intel"
129 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
130 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
133 ### Coreboot layout values
136 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
137 default ROM_IMAGE_SIZE = 65536
140 ## Use a small 8K stack
142 default STACK_SIZE=0x2000
145 ## Use a small 32K heap
147 default HEAP_SIZE=0x8000
151 ### Compute the location and size of where this firmware image
152 ### (coreboot plus bootloader) will live in the boot rom chip.
154 default FALLBACK_SIZE=131072
157 ## coreboot C code runs at this location in RAM
159 default _RAMBASE=0x00004000
162 ## Load the payload from the ROM
164 default CONFIG_ROM_PAYLOAD=1
168 ### Defaults of options that you may want to override in the target config file
172 ## The default compiler
174 default CC="$(CROSS_COMPILE)gcc -m32"
178 ## Disable the gdb stub by default
180 default CONFIG_GDB_STUB=0
183 ## The Serial Console
186 # To Enable the Serial Console
187 default CONFIG_CONSOLE_SERIAL8250=1
189 ## Select the serial console baud rate
190 default TTYS0_BAUD=115200
191 #default TTYS0_BAUD=57600
192 #default TTYS0_BAUD=38400
193 #default TTYS0_BAUD=19200
194 #default TTYS0_BAUD=9600
195 #default TTYS0_BAUD=4800
196 #default TTYS0_BAUD=2400
197 #default TTYS0_BAUD=1200
199 # Select the serial console base port
200 default TTYS0_BASE=0x3f8
202 # Select the serial protocol
203 # This defaults to 8 data bits, 1 stop bit, and no parity
204 default TTYS0_LCS=0x3
207 ### Select the coreboot loglevel
209 ## EMERG 1 system is unusable
210 ## ALERT 2 action must be taken immediately
211 ## CRIT 3 critical conditions
212 ## ERR 4 error conditions
213 ## WARNING 5 warning conditions
214 ## NOTICE 6 normal but significant condition
215 ## INFO 7 informational
216 ## DEBUG 8 debug-level messages
217 ## SPEW 9 way too many details
219 ## Request this level of debugging output
220 default DEFAULT_CONSOLE_LOGLEVEL=5
221 ## At a maximum only compile in this level of debugging
222 default MAXIMUM_CONSOLE_LOGLEVEL=5
225 ## Select power on after power fail setting
226 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
235 default CONFIG_CBFS=0