2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Arastra, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License version 2 as
8 ## published by the Free Software Foundation.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
21 default CONFIG_XIP_ROM_SIZE = 64 * 1024
22 include /config/nofailovercalculation.lb
25 ## Set all of the defaults for an x86 architecture
31 ## Build the objects we have code for in this directory.
35 if CONFIG_GENERATE_MP_TABLE object mptable.o end
36 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
42 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
43 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
46 makerule ./failover.inc
47 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
48 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
52 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
53 action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
56 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
57 action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
61 ## Build our 16 bit and 32 bit coreboot entry code
63 mainboardinit cpu/x86/16bit/entry16.inc
64 mainboardinit cpu/x86/32bit/entry32.inc
65 ldscript /cpu/x86/16bit/entry16.lds
66 ldscript /cpu/x86/32bit/entry32.lds
69 ## Build our reset vector (This is where coreboot is entered)
71 if CONFIG_USE_FALLBACK_IMAGE
72 mainboardinit cpu/x86/16bit/reset16.inc
73 ldscript /cpu/x86/16bit/reset16.lds
75 mainboardinit cpu/x86/32bit/reset32.inc
76 ldscript /cpu/x86/32bit/reset32.lds
79 ### Should this be in the northbridge code?
80 mainboardinit arch/i386/lib/cpu_reset.inc
83 ## Include an id string (For safe flashing)
85 mainboardinit arch/i386/lib/id.inc
86 ldscript /arch/i386/lib/id.lds
89 ### This is the early phase of coreboot startup
90 ### Things are delicate and we test to see if we should
91 ### failover to another image.
93 if CONFIG_USE_FALLBACK_IMAGE
94 ldscript /arch/i386/lib/failover.lds
95 mainboardinit ./failover.inc
99 ### O.k. We aren't just an intermediary anymore!
105 mainboardinit cpu/x86/fpu/enable_fpu.inc
106 mainboardinit cpu/x86/mmx/enable_mmx.inc
107 mainboardinit cpu/x86/sse/enable_sse.inc
108 mainboardinit ./auto.inc
109 mainboardinit cpu/x86/sse/disable_sse.inc
110 mainboardinit cpu/x86/mmx/disable_mmx.inc
113 ## Include the secondary Configuration files
118 chip northbridge/intel/i3100
119 device pci_domain 0 on
120 device pci 00.0 on end # IMCH
121 device pci 00.1 on end # IMCH error status
122 device pci 01.0 on end # IMCH EDMA engine
123 device pci 02.0 on end # PCIe port A/A0
124 device pci 03.0 on end # PCIe port A1
125 device pci 04.0 on end # ?
126 device pci 08.0 off end # must be off to boot
127 device pci 0d.0 off end # must be off to boot
128 device pci 0d.1 off end # must be off to boot
129 chip southbridge/intel/i3100
130 # PIRQ line -> legacy IRQ mappings
131 register "pirq_a_d" = "0x0b070a05"
132 register "pirq_e_h" = "0x0a808080"
134 device pci 1d.0 on end # USB (UHCI)
135 device pci 1d.7 on end # USB (EHCI)
136 device pci 1f.0 on # LPC bridge
137 chip superio/intel/i3100
138 device pnp 4e.4 on # Com1
142 device pnp 4e.5 on # Com2
147 chip superio/smsc/smscsuperio
148 device pnp 2e.0 off end
149 device pnp 2e.3 off end
150 device pnp 2e.4 off end
151 device pnp 2e.5 off end
152 device pnp 2e.7 on # PS/2 keyboard / mouse
155 irq 0x70 = 1 # PS/2 keyboard interrupt
156 irq 0x72 = 12 # PS/2 mouse interrupt
158 device pnp 2e.a off end
161 device pci 1f.2 on end # SATA
162 device pci 1f.3 on end # SMBus
163 device pci 1f.4 on end # ?
166 device apic_cluster 0 on
167 chip cpu/intel/ep80579