2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/mainboard/intel/jarrell/mptable.c */
23 #include <console/console.h>
24 #include <arch/smp/mpspec.h>
25 #include <device/pci.h>
29 void *smp_write_config_table(void *v)
31 static const char sig[4] = "PCMP";
32 static const char oem[8] = "Intel ";
33 static const char productid[12] = "Mt. Arvon ";
34 struct mp_config_table *mc;
39 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
40 memset(mc, 0, sizeof(*mc));
42 memcpy(mc->mpc_signature, sig, sizeof(sig));
43 mc->mpc_length = sizeof(*mc); /* initially just the header */
45 mc->mpc_checksum = 0; /* not yet computed */
46 memcpy(mc->mpc_oem, oem, sizeof(oem));
47 memcpy(mc->mpc_productid, productid, sizeof(productid));
50 mc->mpc_entry_count = 0; /* No entries yet... */
51 mc->mpc_lapic = LAPIC_ADDR;
56 smp_write_processors(mc);
58 /* Define bus numbers */
59 smp_write_bus(mc, 0, "PCI ");
60 smp_write_bus(mc, bus_pci, "PCI ");
61 smp_write_bus(mc, bus_pcie_a, "PCI ");
62 smp_write_bus(mc, bus_isa, "ISA ");
65 smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000);
67 /* ISA backward compatibility interrupts */
68 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
69 bus_isa, 0x00, 0x01, 0x00);
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
71 bus_isa, 0x01, 0x01, 0x01);
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
73 bus_isa, 0x00, 0x01, 0x02);
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
75 bus_isa, 0x03, 0x01, 0x03);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
77 bus_isa, 0x04, 0x01, 0x04);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
79 bus_isa, 0x06, 0x01, 0x06);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
81 bus_isa, 0x08, 0x01, 0x08);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
83 bus_isa, 0x09, 0x01, 0x09);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
85 bus_isa, 0x0c, 0x01, 0x0c);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
87 bus_isa, 0x0d, 0x01, 0x0d);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
89 bus_isa, 0x0e, 0x01, 0x0e);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
91 bus_isa, 0x0f, 0x01, 0x0f);
93 /* Standard local interrupt assignments */
94 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
95 bus_isa, 0x00, MP_APIC_ALL, 0x00);
96 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
97 bus_isa, 0x00, MP_APIC_ALL, 0x01);
99 /* Internal PCI devices */
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
101 0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
103 0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
105 0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
107 0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
109 0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
111 0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
113 0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
115 0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
117 0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
119 0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
121 0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
123 0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
125 0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
129 bus_pci, 0x00, 0x01, 0x10);
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
131 bus_pci, 0x01, 0x01, 0x11);
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
133 bus_pci, 0x02, 0x01, 0x12);
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
135 bus_pci, 0x03, 0x01, 0x13);
137 /* PCIe port A slot */
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
139 bus_pcie_a, 0x00, 0x01, 0x10);
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
141 bus_pcie_a, 0x01, 0x01, 0x11);
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
143 bus_pcie_a, 0x02, 0x01, 0x12);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
145 bus_pcie_a, 0x03, 0x01, 0x13);
147 /* There is no extension information... */
149 /* Compute the checksums */
150 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
152 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
153 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
154 mc, smp_next_mpe_entry(mc));
155 return smp_next_mpe_entry(mc);
158 unsigned long write_smp_table(unsigned long addr)
161 v = smp_write_floating_table(addr);
162 return (unsigned long)smp_write_config_table(v);