src/mainboard/intel/jarrell/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "southbridge/intel/i82801ex/early_smbus.c"
  10 #include "northbridge/intel/e7520/raminit.h"
  11 #include "superio/nsc/pc87427/pc87427.h"
  12 #include "cpu/x86/lapic/boot_cpu.c"
  13 #include "cpu/x86/mtrr/earlymtrr.c"
  14 #include "watchdog.c"
  15 #include "reset.c"
  16 #include "power_reset_check.c"
  17 #include "jarrell_fixups.c"
  18 #include "superio/nsc/pc87427/early_init.c"
  19 #include "northbridge/intel/e7520/memory_initialized.c"
  20 #include "cpu/x86/bist.h"
  21 #include <spd.h>
  22
  23 #define SIO_GPIO_BASE 0x680
  24 #define SIO_XBUS_BASE 0x4880
  25
  26 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  27 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  28
  29 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  30 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  31
  32 static inline int spd_read_byte(unsigned device, unsigned address)
  33 {
  34         return smbus_read_byte(device, address);
  35 }
  36
  37 #include "northbridge/intel/e7520/raminit.c"
  38 #include "lib/generic_sdram.c"
  39 #include "debug.c"
  40 #include "arch/x86/lib/stages.c"
  41
  42 static void main(unsigned long bist)
  43 {
  44         static const struct mem_controller mch[] = {
  45                 {
  46                         .node_id = 0,
  47                         .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
  48                         .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
  49                 }
  50         };
  51
  52         if (bist == 0) {
  53                 /* Skip this if there was a built in self test failure */
  54                 early_mtrr_init();
  55                 if (memory_initialized())
  56                         skip_romstage();
  57         }
  58
  59         /* Setup the console */
  60         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  61         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  62         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  63         /* Enable Serial 2 lines instead of GPIO */
  64         outb(0x2c, 0x2e);
  65         outb((inb(0x2f) & (~1<<1)), 0x2f);
  66         console_init();
  67
  68         /* Halt if there was a built in self test failure */
  69         report_bist_failure(bist);
  70
  71         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  72
  73         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  74         xbus_cfg(PC87427_XBUS_DEV);
  75
  76         /* MOVE ME TO A BETTER LOCATION !!! */
  77         /* config LPC decode for flash memory access */
  78         device_t dev;
  79         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  80         if (dev == PCI_DEV_INVALID)
  81                 die("Missing ich5?");
  82         pci_write_config32(dev, 0xe8, 0x00000000);
  83         pci_write_config8(dev, 0xf0, 0x00);
  84
  85 #if 0
  86         print_pci_devices();
  87 #endif
  88         enable_smbus();
  89 #if 0
  90 //      dump_spd_registers(&cpu[0]);
  91         int i;
  92         for(i = 0; i < 1; i++)
  93                 dump_spd_registers();
  94 #endif
  95         disable_watchdogs();
  96         power_down_reset_check();
  97 //      dump_ipmi_registers();
  98         mainboard_set_e7520_leds();
  99         sdram_initialize(ARRAY_SIZE(mch), mch);
 100         ich5_watchdog_on();
 101 #if 0
 102         dump_pci_devices();
 103         dump_pci_device(PCI_DEV(0, 0x00, 0));
 104         dump_bar14(PCI_DEV(0, 0x00, 0));
 105 #endif
 106 }