src/mainboard/intel/jarrell/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "lib/ramtest.c"
  15 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  16 #include "northbridge/intel/e7520/raminit.h"
  17 #include "superio/nsc/pc87427/pc87427.h"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "watchdog.c"
  21 #include "reset.c"
  22 #include "power_reset_check.c"
  23 #include "jarrell_fixups.c"
  24 #include "superio/nsc/pc87427/pc87427_early_init.c"
  25 #include "northbridge/intel/e7520/memory_initialized.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SIO_GPIO_BASE 0x680
  29 #define SIO_XBUS_BASE 0x4880
  30
  31 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  32 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  33
  34 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  35 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  36
  37 /* Beta values:         0x00090800 */
  38 /* Silver values:       0x000a0900 */
  39 #define RECVENA_CONFIG  0x000a090a
  40 #define RECVENB_CONFIG  0x000a090a
  41 #define DIMM_MAP_LOGICAL 0x0124
  42
  43 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  44 {
  45         /* nothing to do */
  46 }
  47 static inline int spd_read_byte(unsigned device, unsigned address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 #include "northbridge/intel/e7520/raminit.c"
  53 #include "lib/generic_sdram.c"
  54 #include "debug.c"
  55
  56
  57 static void main(unsigned long bist)
  58 {
  59         /*
  60          *
  61          *
  62          */
  63         static const struct mem_controller mch[] = {
  64                 {
  65                         .node_id = 0,
  66                         .f0 = PCI_DEV(0, 0x00, 0),
  67                         .f1 = PCI_DEV(0, 0x00, 1),
  68                         .f2 = PCI_DEV(0, 0x00, 2),
  69                         .f3 = PCI_DEV(0, 0x00, 3),
  70                         .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
  71                         .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
  72                 }
  73         };
  74
  75         if (bist == 0) {
  76                 /* Skip this if there was a built in self test failure */
  77                 early_mtrr_init();
  78                 if (memory_initialized()) {
  79                         asm volatile ("jmp __cpu_reset");
  80                 }
  81         }
  82         /* Setup the console */
  83         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  84         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  85         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  86         /* Enable Serial 2 lines instead of GPIO */
  87         outb(0x2c, 0x2e);
  88         outb((inb(0x2f) & (~1<<1)), 0x2f);
  89         uart_init();
  90         console_init();
  91
  92         /* Halt if there was a built in self test failure */
  93         report_bist_failure(bist);
  94
  95         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  96
  97         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  98         xbus_cfg(PC87427_XBUS_DEV);
  99
 100         /* MOVE ME TO A BETTER LOCATION !!! */
 101         /* config LPC decode for flash memory access */
 102         device_t dev;
 103         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 104         if (dev == PCI_DEV_INVALID) {
 105                 die("Missing ich5?");
 106         }
 107         pci_write_config32(dev, 0xe8, 0x00000000);
 108         pci_write_config8(dev, 0xf0, 0x00);
 109
 110 #if 0
 111         print_pci_devices();
 112 #endif
 113         enable_smbus();
 114 #if 0
 115 //      dump_spd_registers(&cpu[0]);
 116         int i;
 117         for(i = 0; i < 1; i++) {
 118                 dump_spd_registers();
 119         }
 120 #endif
 121         disable_watchdogs();
 122         power_down_reset_check();
 123 //      dump_ipmi_registers();
 124         mainboard_set_e7520_leds();
 125         sdram_initialize(ARRAY_SIZE(mch), mch);
 126         ich5_watchdog_on();
 127 #if 0
 128         dump_pci_devices();
 129 #endif
 130 #if 0
 131         dump_pci_device(PCI_DEV(0, 0x00, 0));
 132         dump_bar14(PCI_DEV(0, 0x00, 0));
 133 #endif
 134
 135 #if 0 // temporarily disabled
 136         /* Check the first 1M */
 137 //      ram_check(0x00000000, 0x000100000);
 138 //      ram_check(0x00000000, 0x000a0000);
 139         ram_check(0x00100000, 0x01000000);
 140         /* check the first 1M in the 3rd Gig */
 141         ram_check(0x30100000, 0x31000000);
 142 #if 0
 143         ram_check(0x00000000, 0x02000000);
 144 #endif
 145
 146 #endif
 147 #if 0
 148         while(1) {
 149                 hlt();
 150         }
 151 #endif
 152 }