1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 struct mp_config_table *mc;
11 unsigned char bus_num;
12 unsigned char bus_isa;
13 unsigned char bus_pxhd_1;
14 unsigned char bus_pxhd_2;
15 unsigned char bus_pxhd_3 = 0;
16 unsigned char bus_pxhd_4 = 0;
17 unsigned char bus_pxhd_x = 0;
18 unsigned char bus_ich5r_1;
19 unsigned int bus_pxhd_id;
21 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
23 mptable_init(mc, "SE7520JR20 ", LAPIC_ADDR);
25 smp_write_processors(mc);
31 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
33 bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
34 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
38 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
44 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
46 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
50 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
55 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
57 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
61 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
65 /* test for active riser with 2nd pxh device */
66 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
68 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
69 if(bus_pxhd_id == 0x35998086) {
70 bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
72 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
74 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
75 if(bus_pxhd_id == 0x03298086) {
76 bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
80 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
82 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
83 if(bus_pxhd_id == 0x032a8086) {
84 bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
91 /* define bus and isa numbers */
92 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
93 smp_write_bus(mc, bus_num, "PCI ");
95 smp_write_bus(mc, bus_isa, "ISA ");
99 smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
101 struct resource *res;
104 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
106 res = find_resource(dev, PCI_BASE_ADDRESS_0);
108 smp_write_ioapic(mc, 0x09, 0x20, res->base);
112 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
115 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
117 res = find_resource(dev, PCI_BASE_ADDRESS_0);
119 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
123 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
127 if(bus_pxhd_3) { /* Active riser pxhd */
128 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
130 res = find_resource(dev, PCI_BASE_ADDRESS_0);
132 smp_write_ioapic(mc, 0x0b, 0x20, res->base);
136 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
140 if(bus_pxhd_4) { /* active riser pxhd */
141 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
143 res = find_resource(dev, PCI_BASE_ADDRESS_0);
145 smp_write_ioapic(mc, 0x0c, 0x20, res->base);
149 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
154 mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
157 bus_isa, 0x0a, 0x08, 0x10);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
159 bus_isa, 0x0b, 0x08, 0x11);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
161 bus_isa, 0x0a, 0x08, 0x10);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
163 bus_isa, 0x07, 0x08, 0x13);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
165 bus_isa, 0x0b, 0x08, 0x12);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
167 bus_isa, 0x05, 0x08, 0x17);
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
169 bus_isa, 0x0b, 0x08, 0x12);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
171 bus_isa, 0x07, 0x08, 0x13);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
173 bus_isa, 0x0b, 0x08, 0x11);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
175 bus_isa, 0x0a, 0x08, 0x10);
177 /* Standard local interrupt assignments */
178 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
179 bus_isa, 0x00, MP_APIC_ALL, 0x00);
180 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
181 bus_isa, 0x00, MP_APIC_ALL, 0x01);
183 /* FIXME verify I have the irqs handled for all of the risers */
185 /* 2:3.0 PCI Slot 1 */
186 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
187 bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
189 bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
190 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
191 bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
192 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
193 bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
196 /* 3:7.0 PCI Slot 2 */
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
198 bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
199 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
200 bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
202 bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
204 bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
206 /* PCI Slot 3 (if active riser) */
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
209 bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
212 /* PCI Slot 4 (if active riser) */
214 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
215 bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
219 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
220 bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
223 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
224 bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
227 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
228 bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
231 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
232 bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
235 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
236 bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
238 /* There is no extension information... */
240 /* Compute the checksums */
241 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
243 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
244 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
245 mc, smp_next_mpe_entry(mc));
246 return smp_next_mpe_entry(mc);
249 unsigned long write_smp_table(unsigned long addr)
252 v = smp_write_floating_table(addr);
253 return (unsigned long)smp_write_config_table(v);