src/mainboard/intel/jarrell/jarrell_fixups.c

   1 #include <arch/romcc_io.h>
   2
   3 static void mch_reset(void)
   4 {
   5         device_t dev;
   6         unsigned long value, base;
   7         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
   8         if (dev != PCI_DEV_INVALID) {
   9                 /* I/O space is always enables */
  10
  11                 /* Set gpio base */
  12                 pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
  13                 base = ICH5_GPIOBASE;
  14
  15                 /* Enable GPIO Bar */
  16                 value = pci_read_config32(dev, 0x5c);
  17                 value |= 0x10;
  18                 pci_write_config32(dev, 0x5c, value);
  19
  20                 /* Set GPIO 19 mux to IO usage */
  21                 value = inl(base);
  22                 value |= (1 <<19);
  23                 outl(value, base);
  24
  25                 /* Pull GPIO 19 low */
  26                 value = inl(base + 0x0c);
  27                 value &= ~(1 << 19);
  28                 outl(value, base + 0x0c);
  29         }
  30         return;
  31 }
  32
  33
  34
  35 static void mainboard_set_e7520_pll(unsigned bits)
  36 {
  37         uint16_t gpio_index;
  38         uint8_t data;
  39         device_t dev;
  40
  41         /* currently only handle the Jarrell/PC87427 case */
  42         dev = PC87427_GPIO_DEV;
  43
  44
  45         pnp_set_logical_device(dev);
  46         gpio_index = pnp_read_iobase(dev, 0x60);
  47
  48         /* select SIO GPIO port 4, pin 2 */
  49         pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
  50         /* set to push-pull, enable output */
  51         pnp_write_config(dev, PC87427_GPCFG1, 0x03);
  52
  53         /* select SIO GPIO port 4, pin 4 */
  54         pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
  55         /* set to push-pull, enable output */
  56         pnp_write_config(dev, PC87427_GPCFG1, 0x03);
  57
  58         /* set gpio 42,44 signal levels */
  59         data = inb(gpio_index + PC87427_GPDO_4);
  60         if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
  61                 print_debug("set_pllsel: correct settings detected!\r\n");
  62                 return; /* settings already configured */
  63         } else {
  64                 outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
  65                 /* reset */
  66                 print_debug("set_pllsel: settings adjusted, now resetting...\r\n");
  67         //      hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
  68 //              mch_reset();
  69                 full_reset();
  70         }
  71         return;
  72 }
  73
  74
  75 static void mainboard_set_e7520_leds(void)
  76 {
  77         uint8_t cnt;
  78         uint8_t data;
  79         device_t dev;
  80
  81         /* currently only handle the Jarrell/PC87427 case */
  82         dev = PC87427_GPIO_DEV;
  83
  84         pnp_set_logical_device(dev);
  85
  86         /* enable */
  87         outb(0x30, 0x2e);
  88         outb(0x01, 0x2f);
  89         outb(0x2d, 0x2e);
  90         outb(0x01, 0x2f);
  91
  92         /* Set auto mode for dimm leds and post */
  93         outb(0xf0,0x2e);
  94         outb(0x70,0x2f);
  95         outb(0xf4,0x2e);
  96         outb(0x30,0x2f);
  97         outb(0xf5,0x2e);
  98         outb(0x88,0x2f);
  99         outb(0xf6,0x2e);
 100         outb(0x00,0x2f);
 101         outb(0xf7,0x2e);
 102         outb(0x90,0x2f);
 103         outb(0xf8,0x2e);
 104         outb(0x00,0x2f);
 105
 106         /* Turn the leds off */
 107         outb(0x00,0x88);
 108         outb(0x00,0x90);
 109
 110         /* Disable the ports */
 111         outb(0xf5,0x2e);
 112         outb(0x00,0x2f);
 113         outb(0xf7,0x2e);
 114         outb(0x00,0x2f);
 115         outb(0xf4,0x2e);
 116         outb(0x00,0x2f);
 117
 118         return;
 119 }
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