1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses CONFIG_MAINBOARD_VENDOR
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
39 uses CONFIG_UDELAY_TSC
40 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
43 uses CONFIG_CONSOLE_SERIAL8250
44 uses CONFIG_TTYS0_BAUD
45 uses CONFIG_TTYS0_BASE
47 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
48 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
49 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
50 uses CONFIG_CONSOLE_BTEXT
53 uses CONFIG_CROSS_COMPILE
55 uses CONFIG_MAX_REBOOT_CNT
56 uses CONFIG_USE_WATCHDOG_ON_BOOT
64 ## Because we do the stutter start we need more attempts
66 default CONFIG_MAX_REBOOT_CNT=8
69 ## Use the watchdog to break out of a lockup condition
71 default CONFIG_USE_WATCHDOG_ON_BOOT=1
74 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
76 default CONFIG_ROM_SIZE=2097152
80 ## Build code for the fallback boot
82 default CONFIG_HAVE_FALLBACK_BOOT=1
85 ## Delay timer options
88 default CONFIG_UDELAY_TSC=1
89 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
92 ## Build code to reset the motherboard from coreboot
94 default CONFIG_HAVE_HARD_RESET=1
97 ## Build code to export a programmable irq routing table
99 default CONFIG_HAVE_PIRQ_TABLE=1
100 default CONFIG_IRQ_SLOT_COUNT=9
103 ## Build code to export an x86 MP table
104 ## Useful for specifying IRQ routing values
106 default CONFIG_HAVE_MP_TABLE=1
109 ## Build code to export a CMOS option table
111 default CONFIG_HAVE_OPTION_TABLE=1
114 ## Move the default coreboot cmos range off of AMD RTC registers
116 default CONFIG_LB_CKS_RANGE_START=49
117 default CONFIG_LB_CKS_RANGE_END=122
118 default CONFIG_LB_CKS_LOC=123
121 ## Build code for SMP support
122 ## Only worry about 2 micro processors
125 default CONFIG_MAX_CPUS=4
126 default CONFIG_LOGICAL_CPUS=0
129 ## Build code to setup a generic IOAPIC
131 default CONFIG_IOAPIC=1
134 ## Clean up the motherboard id strings
136 default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D"
137 default CONFIG_MAINBOARD_VENDOR= "Intel"
138 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
139 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
140 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
143 ### coreboot layout values
146 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
147 default CONFIG_ROM_IMAGE_SIZE = 65536
150 ## Use a small 8K stack
152 default CONFIG_STACK_SIZE=0x2000
155 ## Use a small 32K heap
157 default CONFIG_HEAP_SIZE=0x8000
161 ### Compute the location and size of where this firmware image
162 ### (coreboot plus bootloader) will live in the boot rom chip.
164 default CONFIG_FALLBACK_SIZE=131072
167 ## Coreboot C code runs at this location in RAM
169 default CONFIG_RAMBASE=0x00004000
172 ## Load the payload from the ROM
174 default CONFIG_ROM_PAYLOAD=1
178 ### Defaults of options that you may want to override in the target config file
182 ## The default compiler
184 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
188 ## Disable the gdb stub by default
190 default CONFIG_GDB_STUB=0
193 ## The Serial Console
196 # To Enable the Serial Console
197 default CONFIG_CONSOLE_SERIAL8250=1
199 ## Select the serial console baud rate
200 default CONFIG_TTYS0_BAUD=115200
201 #default CONFIG_TTYS0_BAUD=57600
202 #default CONFIG_TTYS0_BAUD=38400
203 #default CONFIG_TTYS0_BAUD=19200
204 #default CONFIG_TTYS0_BAUD=9600
205 #default CONFIG_TTYS0_BAUD=4800
206 #default CONFIG_TTYS0_BAUD=2400
207 #default CONFIG_TTYS0_BAUD=1200
209 # Select the serial console base port
210 default CONFIG_TTYS0_BASE=0x3f8
212 # Select the serial protocol
213 # This defaults to 8 data bits, 1 stop bit, and no parity
214 default CONFIG_TTYS0_LCS=0x3
217 ### Select the coreboot loglevel
219 ## EMERG 1 system is unusable
220 ## ALERT 2 action must be taken immediately
221 ## CRIT 3 critical conditions
222 ## ERR 4 error conditions
223 ## WARNING 5 warning conditions
224 ## NOTICE 6 normal but significant condition
225 ## INFO 7 informational
226 ## CONFIG_DEBUG 8 debug-level messages
227 ## SPEW 9 Way too many details
229 ## Request this level of debugging output
230 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
231 ## At a maximum only compile in this level of debugging
232 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
235 ## Select power on after power fail setting
236 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
239 ## Don't enable the btext console
241 default CONFIG_CONSOLE_BTEXT=0
249 default CONFIG_CBFS=0