src/mainboard/intel/jarrell/Config.lb

   1 ##
   2 ## Only use the option table in a normal image
   3 ##
   4 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
   5
   6 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   7 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   8 include /config/nofailovercalculation.lb
   9
  10 ##
  11 ## Set all of the defaults for an x86 architecture
  12 ##
  13
  14 arch i386 end
  15
  16 ##
  17 ## Build the objects we have code for in this directory.
  18 ##
  19
  20 driver mainboard.o
  21 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  22 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  23 object reset.o
  24
  25 ##
  26 ## Romcc output
  27 ##
  28 makerule ./failover.E
  29         depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
  30         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
  31 end
  32
  33 makerule ./failover.inc
  34         depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
  35         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
  36 end
  37
  38 makerule ./auto.E
  39         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  40         action  "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  41 end
  42 makerule ./auto.inc
  43         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  44         action  "../romcc    -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  45 end
  46
  47 ##
  48 ## Build our 16 bit and 32 bit coreboot entry code
  49 ##
  50 mainboardinit cpu/x86/16bit/entry16.inc
  51 mainboardinit cpu/x86/32bit/entry32.inc
  52 ldscript /cpu/x86/16bit/entry16.lds
  53 ldscript /cpu/x86/32bit/entry32.lds
  54
  55 ##
  56 ## Build our reset vector (This is where coreboot is entered)
  57 ##
  58 if CONFIG_USE_FALLBACK_IMAGE
  59         mainboardinit cpu/x86/16bit/reset16.inc
  60         ldscript /cpu/x86/16bit/reset16.lds
  61 else
  62         mainboardinit cpu/x86/32bit/reset32.inc
  63         ldscript /cpu/x86/32bit/reset32.lds
  64 end
  65
  66 ### Should this be in the northbridge code?
  67 mainboardinit arch/i386/lib/cpu_reset.inc
  68
  69 ##
  70 ## Include an id string (For safe flashing)
  71 ##
  72 mainboardinit arch/i386/lib/id.inc
  73 ldscript /arch/i386/lib/id.lds
  74
  75 ###
  76 ### This is the early phase of coreboot startup
  77 ### Things are delicate and we test to see if we should
  78 ### failover to another image.
  79 ###
  80 if CONFIG_USE_FALLBACK_IMAGE
  81         ldscript /arch/i386/lib/failover.lds
  82         mainboardinit ./failover.inc
  83 end
  84
  85 ###
  86 ### O.k. We aren't just an intermediary anymore!
  87 ###
  88
  89 ##
  90 ## Setup RAM
  91 ##
  92 mainboardinit cpu/x86/fpu/enable_fpu.inc
  93 mainboardinit cpu/x86/sse/enable_sse.inc
  94 mainboardinit ./auto.inc
  95 mainboardinit cpu/x86/sse/disable_sse.inc
  96 mainboardinit cpu/x86/mmx/disable_mmx.inc
  97
  98 ##
  99 ## Include the secondary Configuration files
 100 ##
 101 dir /pc80
 102 config chip.h
 103
 104 chip northbridge/intel/e7520
 105         device pci_domain 0 on
 106                 device pci 00.0 on end
 107                 device pci 00.1 on end
 108                 device pci 01.0 on end
 109                 device pci 02.0 on
 110                         chip southbridge/intel/pxhd # pxhd1
 111                                 device pci 00.0 on end
 112                                 device pci 00.1 on end
 113                                 device pci 00.2 on
 114                                         chip drivers/generic/generic
 115                                                 device pci 04.0 on end
 116                                                 device pci 04.1 on end
 117                                         end
 118                                 end
 119                                 device pci 00.3 on end
 120                         end
 121                 end
 122                 device pci 06.0 on end
 123                 chip southbridge/intel/i82801er # i82801er
 124                         device pci 1d.0 on end
 125                         device pci 1d.1 on end
 126                         device pci 1d.2 on end
 127                         device pci 1d.3 off end
 128                         device pci 1d.7 on end
 129                         device pci 1e.0 on
 130                                 chip drivers/ati/ragexl
 131                                         device pci 0c.0 on end
 132                                 end
 133                         end
 134                         device pci 1f.0 on
 135                                 chip superio/nsc/pc87427
 136                                         device pnp 2e.0 off end
 137                                         device pnp 2e.2 on
 138 #                                                io 0x60 = 0x2f8
 139 #                                               irq 0x70 = 3
 140                                                  io 0x60 = 0x3f8
 141                                                 irq 0x70 = 4
 142                                         end
 143                                         device pnp 2e.3 on
 144 #                                                io 0x60 = 0x3f8
 145 #                                               irq 0x70 = 4
 146                                                  io 0x60 = 0x2f8
 147                                                 irq 0x70 = 3
 148                                         end
 149                                         device pnp 2e.4 off end
 150                                         device pnp 2e.5 off end
 151                                         device pnp 2e.6 on
 152                                                  io 0x60 = 0x60
 153                                                  io 0x62 = 0x64
 154                                                 irq 0x70 = 1
 155                                         end
 156                                         device pnp 2e.7 off end
 157                                         device pnp 2e.9 off end
 158                                         device pnp 2e.a off end
 159                                         device pnp 2e.f on end
 160                                         device pnp 2e.10 off end
 161                                         device pnp 2e.14 off end
 162                                 end
 163                         end
 164                         device pci 1f.1 on end
 165                         device pci 1f.2 off end
 166                         device pci 1f.3 on end
 167                         device pci 1f.5 off end
 168                         device pci 1f.6 off end
 169                         register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
 170                         register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
 171                         register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
 172                 end
 173         end
 174         device apic_cluster 0 on
 175                 chip cpu/intel/socket_mPGA604 # cpu 0
 176                         device apic 0 on end
 177                 end
 178                 chip cpu/intel/socket_mPGA604 # cpu 1
 179                         device apic 6 on end
 180                 end
 181         end
 182 end