2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
29 #include <arch/romcc_io.h>
30 #include <device/pci_def.h>
31 #include <device/pnp_def.h>
32 #include <cpu/x86/lapic.h>
34 #include "option_table.h"
35 #include "pc80/mc146818rtc_early.c"
37 #include "pc80/serial.c"
38 #include "arch/i386/lib/console.c"
39 #include <cpu/x86/bist.h>
41 #include "lib/ramtest.c"
42 #include "southbridge/intel/i3100/i3100_early_smbus.c"
43 #include "southbridge/intel/i3100/i3100_early_lpc.c"
45 #include "superio/intel/i3100/i3100_early_serial.c"
46 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
66 #define SIO_GPIO_BASE 0x680
67 #define SIO_XBUS_BASE 0x4880
69 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
70 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
72 #define IA32_PERF_STS 0x198
73 #define IA32_PERF_CTL 0x199
74 #define MSR_THERM2_CTL 0x19D
75 #define IA32_MISC_ENABLES 0x1A0
80 #define SATA_MODE_IDE 0x00
81 #define SATA_MODE_AHCI 0x01
85 #define DEFAULT_RCBA 0xFEA00000
87 #define RCBA_RPC 0x0224 /* 32 bit */
89 #define RCBA_TCTL 0x3000 /* 8 bit */
91 #define RCBA_D31IP 0x3100 /* 32 bit */
92 #define RCBA_D30IP 0x3104 /* 32 bit */
93 #define RCBA_D29IP 0x3108 /* 32 bit */
94 #define RCBA_D28IP 0x310C /* 32 bit */
95 #define RCBA_D31IR 0x3140 /* 16 bit */
96 #define RCBA_D30IR 0x3142 /* 16 bit */
97 #define RCBA_D29IR 0x3144 /* 16 bit */
98 #define RCBA_D28IR 0x3146 /* 16 bit */
100 #define RCBA_RTC 0x3400 /* 32 bit */
101 #define RCBA_HPTC 0x3404 /* 32 bit */
102 #define RCBA_GCS 0x3410 /* 32 bit */
103 #define RCBA_BUC 0x3414 /* 8 bit */
104 #define RCBA_FD 0x3418 /* 32 bit */
105 #define RCBA_PRC 0x341C /* 32 bit */
107 static inline void activate_spd_rom(const struct mem_controller *ctrl)
111 static inline int spd_read_byte(u16 device, u8 address)
113 return smbus_read_byte(device, address);
116 #include "northbridge/intel/i3100/raminit.h"
117 #include "cpu/x86/mtrr/earlymtrr.c"
118 #include "northbridge/intel/i3100/memory_initialized.c"
119 #include "northbridge/intel/i3100/raminit.c"
120 #include "lib/generic_sdram.c"
121 #include "northbridge/intel/i3100/reset_test.c"
124 #if CONFIG_USE_FALLBACK_IMAGE == 1
125 #include "southbridge/intel/i3100/cmos_failover.c"
128 void early_config(void) {
133 pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
135 /* Disable watchdog */
136 gcs = read32(DEFAULT_RCBA + RCBA_GCS);
137 gcs |= (1 << 5); /* No reset */
138 write32(DEFAULT_RCBA + RCBA_GCS, gcs);
140 /* Configure PCIe port B as 4x */
141 rpc = read32(DEFAULT_RCBA + RCBA_RPC);
143 write32(DEFAULT_RCBA + RCBA_RPC, rpc);
145 /* Disable Modem, Audio, PCIe ports 2/3/4 */
146 fd = read32(DEFAULT_RCBA + RCBA_FD);
147 fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
148 write32(DEFAULT_RCBA + RCBA_FD, fd);
151 write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
153 /* Improve interrupt routing
154 * D31:F2 SATA INTB# -> PIRQD
155 * D31:F3 SMBUS INTB# -> PIRQD
156 * D31:F4 CHAP INTD# -> PIRQA
157 * D29:F0 USB1#1 INTA# -> PIRQH
158 * D29:F1 USB1#2 INTB# -> PIRQD
159 * D29:F7 USB2 INTA# -> PIRQH
160 * D28:F0 PCIe Port 1 INTA# -> PIRQE
163 write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
164 write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
165 write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
166 write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
168 /* Setup sata mode */
169 pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
172 void real_main(unsigned long bist)
174 /* int boot_mode = 0; */
176 static const struct mem_controller mch[] = {
179 .f0 = PCI_DEV(0, 0x00, 0),
180 .f1 = PCI_DEV(0, 0x00, 1),
181 .f2 = PCI_DEV(0, 0x00, 2),
182 .f3 = PCI_DEV(0, 0x00, 3),
183 .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
184 .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
192 /* Setup the console */
193 i3100_enable_superio();
194 i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
198 /* Halt if there was a built in self test failure */
199 report_bist_failure(bist);
201 /* Perform early board specific init */
204 /* Prevent the TCO timer from rebooting us */
205 i3100_halt_tco_timer();
207 /* Enable SPD ROMs and DDR-II DRAM */
210 /* Enable SpeedStep and automatic thermal throttling */
215 msr = rdmsr(IA32_MISC_ENABLES);
216 msr.lo |= (1 << 3) | (1 << 16);
217 wrmsr(IA32_MISC_ENABLES, msr);
219 /* Set CPU frequency/voltage to maximum */
221 /* Read performance status register and keep
222 * bits 47:32, where BUS_RATIO_MAX and VID_MAX
225 msr = rdmsr(IA32_PERF_STS);
226 perf = msr.hi & 0x0000ffff;
228 /* Write VID_MAX & BUS_RATIO_MAX to
229 * performance control register
231 msr = rdmsr(IA32_PERF_CTL);
232 msr.lo &= 0xffff0000;
234 wrmsr(IA32_PERF_CTL, msr);
237 /* Initialize memory */
238 sdram_initialize(ARRAY_SIZE(mch), mch);
241 /* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
242 #include "cpu/intel/model_6ex/cache_as_ram_disable.c"