2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
23 /* Configuration of the i945 driver */
24 #define CHIPSET_I945GC 1
25 #define CHANNEL_XOR_RANDOMIZATION 1
30 #include <arch/romcc_io.h>
31 #include <device/pci_def.h>
32 #include <device/pnp_def.h>
33 #include <cpu/x86/lapic.h>
35 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
37 #include "option_table.h"
38 #include "pc80/mc146818rtc_early.c"
40 #include <console/console.h>
41 #include "pc80/serial.c"
42 #include "arch/i386/lib/console.c"
43 #include <cpu/x86/bist.h>
45 #if CONFIG_USBDEBUG_DIRECT
46 #define DBGP_DEFAULT 1
47 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
48 #include "pc80/usbdebug_direct_serial.c"
51 #include "lib/ramtest.c"
52 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
53 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
55 #include "northbridge/intel/i945/udelay.c"
57 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
59 #include "southbridge/intel/i82801gx/i82801gx.h"
60 static void setup_ich7_gpios(void)
62 /* TODO: This is highly board specific and should be moved */
63 printk(BIOS_DEBUG, " GPIOS...");
64 /* General Registers */
65 outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
66 outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
67 outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
68 /* Output Control Registers */
69 outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
70 /* Input Control Registers */
71 outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
72 outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
73 outl(0x000000bf, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
74 outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
77 #include "northbridge/intel/i945/early_init.c"
79 static inline int spd_read_byte(unsigned device, unsigned address)
81 return smbus_read_byte(device, address);
84 #include "northbridge/intel/i945/raminit.h"
85 #include "northbridge/intel/i945/raminit.c"
86 #include "northbridge/intel/i945/errata.c"
87 #include "northbridge/intel/i945/debug.c"
89 static void ich7_enable_lpc(void)
92 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
93 // Set COM1/COM2 decode range
94 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
96 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
97 // Enable SuperIO Power Management Events
98 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
102 /* This box has two superios, so enabling serial becomes slightly excessive.
103 * We disable a lot of stuff to make sure that there are no conflicts between
104 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
105 * but safe anyways" method.
107 static void early_superio_config_lpc47m15x(void)
111 dev=PNP_DEV(0x2e, LPC47M15X_SP1);
112 pnp_enter_conf_state(dev);
114 pnp_set_logical_device(dev);
115 pnp_set_enable(dev, 0);
116 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
117 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
118 pnp_set_enable(dev, 1);
120 /* Enable SuperIO PM */
121 dev=PNP_DEV(0x2e, LPC47M15X_PME);
122 pnp_set_logical_device(dev);
123 pnp_set_enable(dev, 0);
124 pnp_set_iobase(dev, PNP_IDX_IO0, 0x680);
125 pnp_set_enable(dev, 1);
127 pnp_exit_conf_state(dev);
130 static void rcba_config(void)
132 /* Set up virtual channel 0 */
133 //RCBA32(0x0014) = 0x80000001;
134 //RCBA32(0x001c) = 0x03128010;
136 /* Device 1f interrupt pin register */
137 RCBA32(0x3100) = 0x00042210;
138 /* Device 1d interrupt pin register */
139 RCBA32(0x310c) = 0x00214321;
141 /* dev irq route register */
142 RCBA16(0x3140) = 0x0132;
143 RCBA16(0x3142) = 0x0146;
144 RCBA16(0x3144) = 0x0237;
145 RCBA16(0x3146) = 0x3201;
146 RCBA16(0x3148) = 0x0146;
149 RCBA8(0x31ff) = 0x03;
151 /* Enable upper 128bytes of CMOS */
152 RCBA32(0x3400) = (1 << 2);
154 /* Disable unused devices */
155 //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
156 // RCBA32(0x3418) |= (1 << 0); // Required.
158 RCBA32(0x3418) = 0x003204e1;
160 /* Enable PCIe Root Port Clock Gate */
161 // RCBA32(0x341c) = 0x00000001;
164 static void early_ich7_init(void)
169 // program secondary mlt XXX byte?
170 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
172 // reset rtc power status
173 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
175 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
177 // usb transient disconnect
178 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
180 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
182 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
183 reg32 |= (1 << 29) | (1 << 17);
184 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
186 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
187 reg32 |= (1 << 31) | (1 << 27);
188 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
190 RCBA32(0x0088) = 0x0011d000;
191 RCBA16(0x01fc) = 0x060f;
192 RCBA32(0x01f4) = 0x86000040;
193 RCBA32(0x0214) = 0x10030549;
194 RCBA32(0x0218) = 0x00020504;
195 RCBA8(0x0220) = 0xc5;
196 reg32 = RCBA32(0x3410);
198 RCBA32(0x3410) = reg32;
199 reg32 = RCBA32(0x3430);
202 RCBA32(0x3430) = reg32;
203 RCBA32(0x3418) |= (1 << 0);
204 RCBA16(0x0200) = 0x2008;
205 RCBA8(0x2027) = 0x0d;
206 RCBA16(0x3e08) |= (1 << 7);
207 RCBA16(0x3e48) |= (1 << 7);
208 RCBA32(0x3e0e) |= (1 << 7);
209 RCBA32(0x3e4e) |= (1 << 7);
211 // next step only on ich7m b0 and later:
212 reg32 = RCBA32(0x2034);
213 reg32 &= ~(0x0f << 16);
215 RCBA32(0x2034) = reg32;
220 // Now, this needs to be included because it relies on the symbol
221 // __PRE_RAM__ being set during CAR stage (in order to compile the
222 // BSS free versions of the functions). Either rewrite the code
223 // to be always BSS free, or invent a flag that's better suited than
224 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
226 #include "lib/cbmem.c"
228 #include "cpu/intel/model_106cx/cache_as_ram_disable.c"
230 void real_main(unsigned long bist)
240 early_superio_config_lpc47m15x();
242 /* Set up the console */
245 #if CONFIG_USBDEBUG_DIRECT
246 i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
247 early_usbdebug_direct_init();
252 /* Halt if there was a built in self test failure */
253 report_bist_failure(bist);
255 if (MCHBAR16(SSKPD) == 0xCAFE) {
256 printk(BIOS_DEBUG, "soft reset detected.\n");
260 /* Perform some early chipset initialization required
261 * before RAM initialization can work
263 i945_early_initialization();
266 reg32 = inl(DEFAULT_PMBASE + 0x04);
267 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
268 if (((reg32 >> 10) & 7) == 5) {
269 #if CONFIG_HAVE_ACPI_RESUME
270 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
272 /* Clear SLP_TYPE. This will break stage2 but
273 * we care for that when we get there.
275 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
277 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
281 /* Enable SPD ROMs and DDR-II DRAM */
284 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
285 dump_spd_registers();
288 sdram_initialize(boot_mode);
290 /* Perform some initialization that must run before stage2 */
293 /* This should probably go away. Until now it is required
294 * and mainboard specific
298 /* Chipset Errata! */
301 /* Initialize the internal PCIe links before we go into stage2 */
302 i945_late_initialization();
304 #if !CONFIG_HAVE_ACPI_RESUME
305 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
306 #if defined(DEBUG_RAM_SETUP)
307 sdram_dump_mchbar_registers();
311 /* This will not work if TSEG is in place! */
312 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
314 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
315 ram_check(0x00000000, 0x000a0000);
316 //ram_check(0x00100000, tom);
321 MCHBAR16(SSKPD) = 0xCAFE;
323 #if CONFIG_HAVE_ACPI_RESUME
324 /* Start address of high memory tables */
325 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
327 /* If there is no high memory area, we didn't boot before, so
328 * this is not a resume. In that case we just create the cbmem toc.
330 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
331 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
333 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
334 * through stage 2. We could keep stuff like stack and heap in high tables
335 * memory completely, but that's a wonderful clean up task for another
338 if (resume_backup_memory)
339 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
341 /* Magic for S3 resume */
342 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);