abfb0b622cfa3eeaec3a153de64048a75f97ad21
[coreboot.git] / src / mainboard / iei / pcisa-lx-800-r10 / Kconfig
1 config BOARD_IEI_PCISA_LX_800_R10
2         bool "PCISA lx-800 r10"
3         select ARCH_X86
4         select CPU_AMD_LX
5         select NORTHBRIDGE_AMD_LX
6         select SOUTHBRIDGE_AMD_CS5536
7         select SUPERIO_WINBOND_W83627HF
8         select HAVE_PIRQ_TABLE
9         select PIRQ_ROUTE
10         select UDELAY_TSC
11         select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
12         select USE_DCACHE_RAM
13         select USE_PRINTK_IN_CAR
14
15 config MAINBOARD_DIR
16         string
17         default iei/pcisa-lx-800-r10 
18         depends on BOARD_IEI_PCISA_LX_800_R10
19
20 config MAINBOARD_PART_NUMBER
21         string
22         default "PCISALX800R10"
23         depends on BOARD_IEI_PCISA_LX_800_R10
24
25 config HAVE_OPTION_TABLE
26         bool
27         default n
28         depends on BOARD_IEI_PCISA_LX_800_R10
29
30 config IRQ_SLOT_COUNT
31         int
32         default 9
33         depends on BOARD_IEI_PCISA_LX_800_R10
34
35 config DCACHE_RAM_BASE
36         hex
37         default 0xc8000
38         depends on BOARD_IEI_PCISA_LX_800_R10
39
40 config DCACHE_RAM_SIZE
41         hex
42         default 0x8000
43         depends on BOARD_IEI_PCISA_LX_800_R10
44
45 config RAMBASE
46         hex
47         default 0x4000
48         depends on BOARD_IEI_PCISA_LX_800_R10
49