2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
18 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
47 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/failover.c ./romcc"
55 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
58 makerule ./failover.inc
59 depends "$(MAINBOARD)/failover.c ./romcc"
60 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
64 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
65 action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
68 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
69 action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
73 ## Build our 16 bit and 32 bit linuxBIOS entry code
75 mainboardinit cpu/x86/16bit/entry16.inc
76 mainboardinit cpu/x86/32bit/entry32.inc
77 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
81 ## Build our reset vector (This is where linuxBIOS is entered)
84 mainboardinit cpu/x86/16bit/reset16.inc
85 ldscript /cpu/x86/16bit/reset16.lds
87 mainboardinit cpu/x86/32bit/reset32.inc
88 ldscript /cpu/x86/32bit/reset32.lds
91 ### Should this be in the northbridge code?
92 mainboardinit arch/i386/lib/cpu_reset.inc
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
101 ### This is the early phase of linuxBIOS startup
102 ### Things are delicate and we test to see if we should
103 ### failover to another image.
105 if USE_FALLBACK_IMAGE
106 ldscript /arch/i386/lib/failover.lds
107 mainboardinit ./failover.inc
111 ### O.k. We aren't just an intermediary anymore!
117 mainboardinit cpu/x86/fpu/enable_fpu.inc
118 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
119 mainboardinit cpu/amd/model_gx1/gx_setup.inc
120 mainboardinit ./auto.inc
123 ## Include the secondary Configuration files
128 chip northbridge/amd/gx1
129 device pci_domain 0 on
130 device pci 0.0 on end
131 chip southbridge/amd/cs5530
132 register "audio_irq" = "5"
133 register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
134 register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
135 register "unwanted_vpci[2]" = "0" # End of list has a zero
138 chip superio/winbond/w83977tf
139 device pnp 2e.0 on # Keyboard
144 device pnp 2e.1 on # Mouse
147 device pnp 2e.2 on # RTC
151 device pnp 2e.3 off # FDC
153 device pnp 2e.4 on # Parallel Port
157 device pnp 2e.5 on # COM2
161 device pnp 2e.6 on # COM1
165 device pnp 2e.7 on # GPIO
168 device pnp 2e.8 on # Power Management
171 register "com1" = "{115200}"
172 register "com2" = "{115200}"
174 device pci 12.1 on end # SMI
175 device pci 12.2 on end # IDE
176 device pci 12.3 on end # Audio
182 chip drivers/pci/onboard
183 device pci 12.4 on end
184 register "rom_address" = "0xfffc0000" #256k image
185 #register "rom_address" = "0xfff80000" #512k image
186 #register "rom_address" = "0xfff00000" #1M image
190 device pci 0a.0 on end # ETH0
191 device pci 0b.0 on end # ETH1
192 device pci 0c.0 on end # ETH2
193 device pci 0f.0 on end # ETH3
195 device pci 13.0 on # USB
201 chip cpu/amd/model_gx1