2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 //#define SYSTEM_TYPE 0 /* SERVER */
21 #define SYSTEM_TYPE 1 /* DESKTOP */
22 //#define SYSTEM_TYPE 2 /* MOBILE */
24 #define SET_NB_CFG_54 1
27 #define QRANK_DIMM_SUPPORT 1
29 //used by incoherent_ht
30 #define FAM10_SCAN_PCI_BUS 0
31 #define FAM10_ALLOCATE_IO_RANGE 0
33 //used by init_cpus and fidvid
35 #define SET_FIDVID_CORE_RANGE 0
37 /* UART address and device number */
38 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
42 #include <device/pci_def.h>
43 #include <device/pci_ids.h>
45 #include <device/pnp_def.h>
46 #include <arch/romcc_io.h>
47 #include <cpu/x86/lapic.h>
48 #include <console/console.h>
49 #include <cpu/amd/model_10xxx_rev.h>
50 #include "northbridge/amd/amdfam10/raminit.h"
51 #include "northbridge/amd/amdfam10/amdfam10.h"
54 #include "cpu/x86/lapic/boot_cpu.c"
55 #include "northbridge/amd/amdfam10/reset_test.c"
57 #include <console/loglevel.h>
58 #include "cpu/x86/bist.h"
60 static int smbus_read_byte(u32 device, u32 address);
62 #include "superio/fintek/f71859/f71859_early_serial.c"
65 #include "cpu/x86/mtrr/earlymtrr.c"
66 #include <cpu/amd/mtrr.h>
67 #include "northbridge/amd/amdfam10/setup_resource_map.c"
69 #include "southbridge/amd/rs780/rs780_early_setup.c"
70 #include "southbridge/amd/sb700/sb700_early_setup.c"
71 #include "northbridge/amd/amdfam10/debug.c"
73 static void activate_spd_rom(const struct mem_controller *ctrl)
77 static int spd_read_byte(u32 device, u32 address)
80 result = smbus_read_byte(device, address);
84 #include "northbridge/amd/amdfam10/amdfam10.h"
86 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
87 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
89 #include "resourcemap.c"
90 #include "cpu/amd/quadcore/quadcore.c"
92 #include "cpu/amd/car/post_cache_as_ram.c"
93 #include "cpu/amd/microcode/microcode.c"
94 #include "cpu/amd/model_10xxx/update_microcode.c"
95 #include "cpu/amd/model_10xxx/init_cpus.c"
97 #include "northbridge/amd/amdfam10/early_ht.c"
98 #include "southbridge/amd/sb700/sb700_early_setup.c"
100 //#include "spd_addr.h"
110 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
113 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
114 static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
119 if (!cpu_init_detectedx && boot_cpu()) {
120 /* Nothing special needs to be done to find bus 0 */
121 /* Allow the HT devices to be found */
122 /* mov bsp to bus 0xff when > 8 nodes */
123 set_bsp_node_CHtExtNodeCfgEn();
124 enumerate_ht_chain();
132 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
133 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
141 f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
145 sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
146 early_usbdebug_init();
150 printk(BIOS_DEBUG, "\n");
152 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
154 /* Halt if there was a built in self test failure */
155 report_bist_failure(bist);
159 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
160 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
161 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
162 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
164 /* Setup sysinfo defaults */
165 set_sysinfo_in_ram(0);
167 update_microcode(val);
173 amd_ht_init(sysinfo);
176 /* Setup nodes PCI space and start core 0 AP init. */
177 finalize_node_setup(sysinfo);
179 /* Setup any mainboard PCI settings etc. */
180 setup_mb_resource_map();
183 /* wait for all the APs core0 started by finalize_node_setup. */
184 /* FIXME: A bunch of cores are going to start output to serial at once.
185 It would be nice to fixup prink spinlocks for ROM XIP mode.
186 I think it could be done by putting the spinlock flag in the cache
187 of the BSP located right after sysinfo.
189 wait_all_core0_started();
191 #if CONFIG_LOGICAL_CPUS==1
192 /* Core0 on each node is configured. Now setup any additional cores. */
193 printk(BIOS_DEBUG, "start_other_cores()\n");
196 wait_all_other_cores_started(bsp_apicid);
201 /* run _early_setup before soft-reset. */
206 msr = rdmsr(0xc0010071);
207 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
209 /* FIXME: The sb fid change may survive the warm reset and only
210 need to be done once.*/
211 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
215 if (!warm_reset_detect(0)) { // BSP is node 0
216 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
218 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
223 /* show final fid and vid */
224 msr=rdmsr(0xc0010071);
225 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
230 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
231 if (!warm_reset_detect(0)) {
232 print_info("...WARM RESET...\n\n\n");
234 die("After soft_reset_x - shouldn't see this message!!!\n");
239 /* It's the time to set ctrl in sysinfo now; */
240 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
241 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
245 // die("Die Before MCT init.");
247 printk(BIOS_DEBUG, "raminit_amdmct()\n");
248 raminit_amdmct(sysinfo);
252 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
253 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
254 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
255 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
258 // ram_check(0x00200000, 0x00200000 + (640 * 1024));
259 // ram_check(0x40200000, 0x40200000 + (640 * 1024));
261 // die("After MCT init before CAR disabled.");
263 rs780_before_pci_init();
264 sb700_before_pci_init();
267 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
268 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
269 post_code(0x43); // Should never see this post code.