2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 Name(_ADR, 0x00140001)
31 /* Some timing tables */
32 Name(UDTT, Package(){ /* Udma timing table */
33 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
36 Name(MDTT, Package(){ /* MWDma timing table */
37 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
40 Name(POTT, Package(){ /* Pio timing table */
41 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
44 /* Some timing register value tables */
45 Name(MDRT, Package(){ /* MWDma timing register table */
46 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
50 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
53 OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
54 Field(ICRG, AnyAcc, NoLock, Preserve)
56 PPTS, 8, /* Primary PIO Slave Timing */
57 PPTM, 8, /* Primary PIO Master Timing */
58 OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
59 PMTM, 8, /* Primary MWDMA Master Timing */
60 OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
61 OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
62 PPSM, 4, /* Primary PIO slave Mode */
63 OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
64 OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
65 PDSM, 4, /* Primary UltraDMA Mode */
68 Method(GTTM, 1) /* get total time*/
70 Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
72 Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
74 Return(Multiply(30, Add(Local0, Local1)))
82 NAME(OTBF, Buffer(20) { /* out buffer */
83 0xFF, 0xFF, 0xFF, 0xFF,
84 0xFF, 0xFF, 0xFF, 0xFF,
85 0xFF, 0xFF, 0xFF, 0xFF,
86 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
89 CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
90 CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
91 CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
92 CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
93 CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
95 /* Just return if the channel is disabled */
96 If(And(PPCR, 0x01)) { /* primary PIO control */
100 /* Always tell them independent timing available and IOChannelReady used on both drives */
103 Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
104 Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
106 If(And(PDCR, 0x01)) { /* It's under UDMA mode */
108 Store(DerefOf(Index(UDTT, PDMM)), DSD0)
111 Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
114 If(And(PDCR, 0x02)) { /* It's under UDMA mode */
116 Store(DerefOf(Index(UDTT, PDSM)), DSD1)
119 Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
122 Return(OTBF) /* out buffer */
123 } /* End Method(_GTM) */
125 Method(_STM, 3, NotSerialized)
127 NAME(INBF, Buffer(20) { /* in buffer */
128 0xFF, 0xFF, 0xFF, 0xFF,
129 0xFF, 0xFF, 0xFF, 0xFF,
130 0xFF, 0xFF, 0xFF, 0xFF,
131 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
134 CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
135 CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
136 CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
137 CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
138 CreateDwordField(INBF, 16, BFFG) /*buffer flag */
140 Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
141 Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
142 Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
143 Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
145 Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
146 Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
148 If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
149 Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
150 Divide(Local0, 7, PDMM,)
154 If(LNotEqual(DSD0, 0xFFFFFFFF)) {
155 Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
156 Store(DerefOf(Index(MDRT, Local0)), PMTM)
160 If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
161 Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
162 Divide(Local0, 7, PDSM,)
166 If(LNotEqual(DSD1, 0xFFFFFFFF)) {
167 Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
168 Store(DerefOf(Index(MDRT, Local0)), PMTS)
172 } /*End Method(_STM) */
177 Name(CMBF, Buffer(21) {
178 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
179 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
182 CreateByteField(CMBF, 1, POMD)
183 CreateByteField(CMBF, 8, DMMD)
184 CreateByteField(CMBF, 5, CMDA)
185 CreateByteField(CMBF, 12, CMDB)
186 CreateByteField(CMBF, 19, CMDC)
194 If(And(PDCR, 0x01)) {
199 (MDTT, MLE, GTTM(PMTM),
201 If(LLess(Local0, 3)) {
202 Or(0x20, Local0, DMMD)
207 } /* End Device(MST) */
213 Name(CMBF, Buffer(21) {
214 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
215 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
216 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
218 CreateByteField(CMBF, 1, POMD)
219 CreateByteField(CMBF, 8, DMMD)
220 CreateByteField(CMBF, 5, CMDA)
221 CreateByteField(CMBF, 12, CMDB)
222 CreateByteField(CMBF, 19, CMDC)
230 If(And(PDCR, 0x02)) {
235 (MDTT, MLE, GTTM(PMTS),
237 If(LLess(Local0, 3)) {
238 Or(0x20, Local0, DMMD)
243 } /* End Device(SLAV) */