2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
5 default ROM_SIZE = 256 * 1024
6 default ROM_SECTION_SIZE = ROM_SIZE
7 default ROM_SECTION_OFFSET = 0
10 ## Compute the start location and size size of
11 ## The linuxBIOS bootloader.
13 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
14 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
17 ## Compute where this copy of linuxBIOS will start in the boot rom
19 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
22 ## Compute a range of ROM that can cached to speed up linuxBIOS,
25 ## XIP_ROM_SIZE must be a power of 2.
26 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
28 default XIP_ROM_SIZE=65536
29 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
32 ## Set all of the defaults for an x86 architecture
38 ## Build the objects we have code for in this directory.
43 if HAVE_PIRQ_TABLE object irq_tables.o end
50 depends "$(MAINBOARD)/failover.c ./romcc"
51 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
54 makerule ./failover.inc
55 depends "$(MAINBOARD)/failover.c ./romcc"
56 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
60 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
61 action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
64 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
65 action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
69 ## Build our 16 bit and 32 bit linuxBIOS entry code
71 mainboardinit cpu/x86/16bit/entry16.inc
72 mainboardinit cpu/x86/32bit/entry32.inc
73 ldscript /cpu/x86/16bit/entry16.lds
74 ldscript /cpu/x86/32bit/entry32.lds
77 ## Build our reset vector (This is where linuxBIOS is entered)
79 mainboardinit cpu/x86/16bit/reset16.inc
80 ldscript /cpu/x86/16bit/reset16.lds
82 ### Should this be in the northbridge code?
83 mainboardinit arch/i386/lib/cpu_reset.inc
86 ## Include an id string (For safe flashing)
88 mainboardinit arch/i386/lib/id.inc
89 ldscript /arch/i386/lib/id.lds
92 ### O.k. We aren't just an intermediary anymore!
98 mainboardinit cpu/x86/fpu/enable_fpu.inc
99 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
100 mainboardinit cpu/amd/model_gx1/gx_setup.inc
101 mainboardinit ./auto.inc
104 ## Include the secondary Configuration files
109 chip northbridge/amd/gx1
110 device pci_domain 0 on
111 device pci 0.0 on end
112 chip southbridge/amd/cs5530
115 chip superio/winbond/w83977f
116 device pnp 3f0.0 on # FDC
119 device pnp 3f0.1 on # Parallel port
123 device pnp 3f0.2 on # COM1
127 register "com1" = "{115200}"
128 device pnp 3f0.3 on # COM2
132 register "com2" = "{115200}"
133 device pnp 3f0.4 on # RTC
137 device pnp 3f0.5 on # Keyboard
140 irq 0x70 = 1 # Int 1 for PS/2 keyboard
141 irq 0x72 = 12 # Int 12 for PS/2 mouse
143 device pnp 3f0.6 off # IR
145 device pnp 3f0.7 off # GPIO1
147 device pnp 3f0.8 off # GPIO
150 device pci 12.1 on end # SMI
151 device pci 12.2 on end # IDE
152 device pci 12.3 on end # Audio
153 device pci 12.4 on end # VGA onboard
157 device pci 0e.0 on end # ETH0
158 device pci 13.0 on end # USB
163 chip cpu/amd/model_gx1