src/mainboard/ibm/e326/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include <pc80/mc146818rtc.h>
  11 #include <console/console.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  31
  32 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  33
  34 static void memreset_setup(void)
  35 {
  36         if (is_cpu_pre_c0()) {
  37                 /* Set the memreset low */
  38                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  39                 /* Ensure the BIOS has control of the memory lines */
  40                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  41         } else {
  42                 /* Ensure the CPU has controll of the memory lines */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44         }
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49         if (is_cpu_pre_c0()) {
  50                 udelay(800);
  51                 /* Set memreset_high */
  52                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  53                 udelay(90);
  54         }
  55 }
  56
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59         /* nothing to do */
  60 }
  61
  62 static inline int spd_read_byte(unsigned device, unsigned address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "resourcemap.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72
  73 #if CONFIG_LOGICAL_CPUS==1
  74 #define SET_NB_CFG_54 1
  75 #endif
  76 #include "cpu/amd/dualcore/dualcore.c"
  77
  78 #define FIRST_CPU  1
  79 #define SECOND_CPU 1
  80 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  81
  82
  83
  84 #include "cpu/amd/car/post_cache_as_ram.c"
  85
  86 #include "cpu/amd/model_fxx/init_cpus.c"
  87
  88 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  89 #include "northbridge/amd/amdk8/early_ht.c"
  90
  91 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  92 {
  93         static const struct mem_controller cpu[] = {
  94                 {
  95                         .node_id = 0,
  96                         .f0 = PCI_DEV(0, 0x18, 0),
  97                         .f1 = PCI_DEV(0, 0x18, 1),
  98                         .f2 = PCI_DEV(0, 0x18, 2),
  99                         .f3 = PCI_DEV(0, 0x18, 3),
 100                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 101                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 102                 },
 103 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 104                 {
 105                         .node_id = 1,
 106                         .f0 = PCI_DEV(0, 0x19, 0),
 107                         .f1 = PCI_DEV(0, 0x19, 1),
 108                         .f2 = PCI_DEV(0, 0x19, 2),
 109                         .f3 = PCI_DEV(0, 0x19, 3),
 110                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 111                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 112                 },
 113 #endif
 114         };
 115
 116         int needs_reset;
 117
 118         if (!cpu_init_detectedx && boot_cpu()) {
 119                 /* Nothing special needs to be done to find bus 0 */
 120                 /* Allow the HT devices to be found */
 121
 122                 enumerate_ht_chain();
 123
 124                 amd8111_enable_rom();
 125         }
 126
 127         if (bist == 0) {
 128                 init_cpus(cpu_init_detectedx);
 129         }
 130
 131         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 132         uart_init();
 133         console_init();
 134
 135         /* Halt if there was a built in self test failure */
 136         report_bist_failure(bist);
 137
 138         setup_ibm_e326_resource_map();
 139
 140         needs_reset = setup_coherent_ht_domain();
 141
 142 #if CONFIG_LOGICAL_CPUS==1
 143         // It is said that we should start core1 after all core0 launched
 144         start_other_cores();
 145 #endif
 146         // automatically set that for you, but you might meet tight space
 147         needs_reset |= ht_setup_chains_x();
 148
 149         if (needs_reset) {
 150                 print_info("ht reset -\n");
 151                 soft_reset();
 152         }
 153
 154         enable_smbus();
 155
 156         memreset_setup();
 157         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 158
 159         post_cache_as_ram();
 160
 161 }
 162