src/mainboard/ibm/e326/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #if CONFIG_USE_INIT == 0
  24 #include "lib/memcpy.c"
  25 #endif
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  31
  32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  38
  39 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  40
  41 static void memreset_setup(void)
  42 {
  43         if (is_cpu_pre_c0()) {
  44                 /* Set the memreset low */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  46                 /* Ensure the BIOS has control of the memory lines */
  47                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  48         } else {
  49                 /* Ensure the CPU has controll of the memory lines */
  50                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  51         }
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56         if (is_cpu_pre_c0()) {
  57                 udelay(800);
  58                 /* Set memreset_high */
  59                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  60                 udelay(90);
  61         }
  62 }
  63
  64
  65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  66 {
  67         /* nothing to do */
  68 }
  69
  70 static inline int spd_read_byte(unsigned device, unsigned address)
  71 {
  72         return smbus_read_byte(device, address);
  73 }
  74
  75 #define QRANK_DIMM_SUPPORT 1
  76
  77 #include "northbridge/amd/amdk8/raminit.c"
  78 #include "resourcemap.c"
  79 #include "northbridge/amd/amdk8/coherent_ht.c"
  80 #include "sdram/generic_sdram.c"
  81
  82 #if CONFIG_LOGICAL_CPUS==1
  83 #define SET_NB_CFG_54 1
  84 #endif
  85 #include "cpu/amd/dualcore/dualcore.c"
  86
  87 #define FIRST_CPU  1
  88 #define SECOND_CPU 1
  89 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  90
  91 #include "cpu/amd/car/copy_and_run.c"
  92
  93 #include "cpu/amd/car/post_cache_as_ram.c"
  94
  95 #include "cpu/amd/model_fxx/init_cpus.c"
  96
  97
  98 #if USE_FALLBACK_IMAGE == 1
  99
 100 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 101 #include "northbridge/amd/amdk8/early_ht.c"
 102
 103 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 104 {
 105         unsigned last_boot_normal_x = last_boot_normal();
 106
 107         /* Is this a cpu only reset? or Is this a secondary cpu? */
 108         if ((cpu_init_detectedx) || (!boot_cpu())) {
 109                 if (last_boot_normal_x) {
 110                         goto normal_image;
 111                 } else {
 112                         goto fallback_image;
 113                 }
 114         }
 115
 116         /* Nothing special needs to be done to find bus 0 */
 117         /* Allow the HT devices to be found */
 118
 119         enumerate_ht_chain();
 120
 121         amd8111_enable_rom();
 122
 123         /* Is this a deliberate reset by the bios */
 124         if (bios_reset_detected() && last_boot_normal_x) {
 125                 goto normal_image;
 126         }
 127         /* This is the primary cpu how should I boot? */
 128         else if (do_normal_boot()) {
 129                 goto normal_image;
 130         }
 131         else {
 132                 goto fallback_image;
 133         }
 134  normal_image:
 135         __asm__ volatile ("jmp __normal_image"
 136                 : /* outputs */
 137                 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
 138                 );
 139
 140  fallback_image:
 141         ;
 142 }
 143 #endif
 144
 145 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 146
 147 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 148 {
 149
 150 #if USE_FALLBACK_IMAGE == 1
 151         failover_process(bist, cpu_init_detectedx);
 152 #endif
 153         real_main(bist, cpu_init_detectedx);
 154
 155 }
 156
 157 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 158 {
 159         static const struct mem_controller cpu[] = {
 160                 {
 161                         .node_id = 0,
 162                         .f0 = PCI_DEV(0, 0x18, 0),
 163                         .f1 = PCI_DEV(0, 0x18, 1),
 164                         .f2 = PCI_DEV(0, 0x18, 2),
 165                         .f3 = PCI_DEV(0, 0x18, 3),
 166                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 167                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 168                 },
 169 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 170                 {
 171                         .node_id = 1,
 172                         .f0 = PCI_DEV(0, 0x19, 0),
 173                         .f1 = PCI_DEV(0, 0x19, 1),
 174                         .f2 = PCI_DEV(0, 0x19, 2),
 175                         .f3 = PCI_DEV(0, 0x19, 3),
 176                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 177                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 178                 },
 179 #endif
 180         };
 181
 182         int needs_reset;
 183
 184         if (bist == 0) {
 185                 init_cpus(cpu_init_detectedx);
 186         }
 187
 188         pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
 189         uart_init();
 190         console_init();
 191
 192         /* Halt if there was a built in self test failure */
 193         report_bist_failure(bist);
 194
 195         setup_ibm_e326_resource_map();
 196
 197         needs_reset = setup_coherent_ht_domain();
 198
 199 #if CONFIG_LOGICAL_CPUS==1
 200         // It is said that we should start core1 after all core0 launched
 201         start_other_cores();
 202 #endif
 203         // automatically set that for you, but you might meet tight space
 204         needs_reset |= ht_setup_chains_x();
 205
 206         if (needs_reset) {
 207                 print_info("ht reset -\r\n");
 208                 soft_reset();
 209         }
 210
 211         enable_smbus();
 212
 213         memreset_setup();
 214         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 215
 216         post_cache_as_ram();
 217
 218 }