src/mainboard/ibm/e326/auto.c

   1 #define ASSEMBLY 1
   2 #define DEFAULT_CONSOLE_LOGLEVEL 8
   3 #define MAXIMUM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <arch/cpu.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "ram/ramtest.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include <cpu/amd/model_fxx_rev.h>
  25 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  26 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  30
  31 static void hard_reset(void)
  32 {
  33         set_bios_reset();
  34
  35         /* enable cf9 */
  36         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  37         /* reset */
  38         outb(0x0e, 0x0cf9);
  39 }
  40
  41 static void soft_reset(void)
  42 {
  43         set_bios_reset();
  44         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  45 }
  46
  47 static void memreset_setup(void)
  48 {
  49         if (is_cpu_pre_c0()) {
  50                 /* Set the memreset low */
  51                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  52                 /* Ensure the BIOS has control of the memory lines */
  53                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  54         } else {
  55                 /* Ensure the CPU has controll of the memory lines */
  56                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  57         }
  58 }
  59
  60 static void memreset(int controllers, const struct mem_controller *ctrl)
  61 {
  62         if (is_cpu_pre_c0()) {
  63                 udelay(800);
  64                 /* Set memreset_high */
  65                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  66                 udelay(90);
  67         }
  68 }
  69
  70 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  71 {
  72         /* nothing to do */
  73 }
  74
  75 static inline int spd_read_byte(unsigned device, unsigned address)
  76 {
  77         return smbus_read_byte(device, address);
  78 }
  79
  80 #include "northbridge/amd/amdk8/raminit.c"
  81
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "northbridge/amd/amdk8/incoherent_ht.c"
  84 #include "sdram/generic_sdram.c"
  85 #include "mainboard/ibm/e326/resourcemap.c"
  86 #include "cpu/amd/dualcore/dualcore.c"
  87
  88 #define FIRST_CPU  1
  89 #define SECOND_CPU 1
  90 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  91 static void main(unsigned long bist)
  92 {
  93         static const struct mem_controller cpu[] = {
  94 #if FIRST_CPU
  95                 {
  96                         .node_id = 0,
  97                         .f0 = PCI_DEV(0, 0x18, 0),
  98                         .f1 = PCI_DEV(0, 0x18, 1),
  99                         .f2 = PCI_DEV(0, 0x18, 2),
 100                         .f3 = PCI_DEV(0, 0x18, 3),
 101                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 102                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 103                 },
 104 #endif
 105 #if SECOND_CPU
 106                 {
 107                         .node_id = 1,
 108                         .f0 = PCI_DEV(0, 0x19, 0),
 109                         .f1 = PCI_DEV(0, 0x19, 1),
 110                         .f2 = PCI_DEV(0, 0x19, 2),
 111                         .f3 = PCI_DEV(0, 0x19, 3),
 112                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 113                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 114                 },
 115 #endif
 116         };
 117
 118         int needs_reset;
 119         unsigned nodeid;
 120
 121         if (bist == 0) {
 122                 k8_init_and_stop_secondaries();
 123         }
 124         /* Setup the console */
 125         pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
 126         uart_init();
 127         console_init();
 128
 129         /* Halt if there was a built in self test failure */
 130         report_bist_failure(bist);
 131
 132 #if 0
 133         print_pci_devices();
 134 #endif
 135
 136         setup_ibm_e326_resource_map();
 137
 138 #if 0
 139         print_debug("after setting resource\n");
 140         print_pci_devices();
 141 #endif
 142
 143         needs_reset = setup_coherent_ht_domain();
 144         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
 145
 146 #if 0
 147         print_debug("after ht stuff\n");
 148         print_pci_devices();
 149 #endif
 150
 151         if (needs_reset) {
 152                 print_info("ht reset -\r\n");
 153                 soft_reset();
 154         }
 155
 156 #if 0
 157         print_pci_devices();
 158 #endif
 159
 160         enable_smbus();
 161
 162 #if 0
 163         dump_spd_registers(&cpu[0]);
 164 #endif
 165
 166         memreset_setup();
 167         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 168
 169 #if 0
 170         dump_pci_devices();
 171 #endif
 172
 173 #if 0
 174         dump_pci_device(PCI_DEV(0, 0x18, 2));
 175 #endif
 176
 177 #if 0
 178         /* Check the first 1M */
 179         ram_check(0x00000000, 0x001000000);
 180 #endif
 181 }