src/mainboard/ibm/e326/auto.c

   1 #define ASSEMBLY 1
   2 #define DEFAULT_CONSOLE_LOGLEVEL 8
   3 #define MAXIMUM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <arch/cpu.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include <cpu/amd/model_fxx_rev.h>
  24 #include "superio/NSC/pc87366/pc87366_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void memreset_setup(void)
  47 {
  48         if (is_cpu_pre_c0()) {
  49                 /* Set the memreset low */
  50                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  51                 /* Ensure the BIOS has control of the memory lines */
  52                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  53         } else {
  54                 /* Ensure the CPU has controll of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  56         }
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61         if (is_cpu_pre_c0()) {
  62                 udelay(800);
  63                 /* Set memreset_high */
  64                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  65                 udelay(90);
  66         }
  67 }
  68
  69 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  70 {
  71         /* Routing Table Node i
  72          *
  73          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  74          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  75          *
  76          * [ 0: 3] Request Route
  77          *     [0] Route to this node
  78          *     [1] Route to Link 0
  79          *     [2] Route to Link 1
  80          *     [3] Route to Link 2
  81          * [11: 8] Response Route
  82          *     [0] Route to this node
  83          *     [1] Route to Link 0
  84          *     [2] Route to Link 1
  85          *     [3] Route to Link 2
  86          * [19:16] Broadcast route
  87          *     [0] Route to this node
  88          *     [1] Route to Link 0
  89          *     [2] Route to Link 1
  90          *     [3] Route to Link 2
  91          */
  92
  93         uint32_t ret = 0x00010101; /* default row entry */
  94
  95         /* CPU0 LDT2 <-> LDT2 CPU1 */
  96         static const unsigned int rows_2p[2][2] = {
  97                 { 0x00090101, 0x00010808 },
  98                 { 0x00010808, 0x00090101 }
  99         };
 100
 101         if (maxnodes > 2) {
 102                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 103                 maxnodes = 2;
 104         }
 105
 106         if (!(node >= maxnodes || row >= maxnodes)) {
 107                 ret = rows_2p[node][row];
 108         }
 109
 110         return ret;
 111 }
 112
 113 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 114 {
 115         /* nothing to do */
 116 }
 117
 118 static inline int spd_read_byte(unsigned device, unsigned address)
 119 {
 120         return smbus_read_byte(device, address);
 121 }
 122
 123 #include "northbridge/amd/amdk8/raminit.c"
 124
 125 #include "northbridge/amd/amdk8/coherent_ht.c"
 126 #include "northbridge/amd/amdk8/incoherent_ht.c"
 127 #include "sdram/generic_sdram.c"
 128 #include "mainboard/ibm/e326/resourcemap.c"
 129 #include "cpu/amd/dualcore/dualcore.c"
 130
 131 #define FIRST_CPU  1
 132 #define SECOND_CPU 1
 133 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 134 static void main(unsigned long bist)
 135 {
 136         static const struct mem_controller cpu[] = {
 137 #if FIRST_CPU
 138                 {
 139                         .node_id = 0,
 140                         .f0 = PCI_DEV(0, 0x18, 0),
 141                         .f1 = PCI_DEV(0, 0x18, 1),
 142                         .f2 = PCI_DEV(0, 0x18, 2),
 143                         .f3 = PCI_DEV(0, 0x18, 3),
 144                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 145                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 146                 },
 147 #endif
 148 #if SECOND_CPU
 149                 {
 150                         .node_id = 1,
 151                         .f0 = PCI_DEV(0, 0x19, 0),
 152                         .f1 = PCI_DEV(0, 0x19, 1),
 153                         .f2 = PCI_DEV(0, 0x19, 2),
 154                         .f3 = PCI_DEV(0, 0x19, 3),
 155                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 156                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 157                 },
 158 #endif
 159         };
 160
 161         int needs_reset;
 162         unsigned nodeid;
 163
 164         if (bist == 0) {
 165                 k8_init_and_stop_secondaries();
 166         }
 167         /* Setup the console */
 168         pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
 169         uart_init();
 170         console_init();
 171
 172         /* Halt if there was a built in self test failure */
 173         report_bist_failure(bist);
 174
 175 #if 0
 176         print_pci_devices();
 177 #endif
 178
 179         setup_ibm_e326_resource_map();
 180
 181 #if 0
 182         print_debug("after setting resource\n");
 183         print_pci_devices();
 184 #endif
 185
 186         needs_reset = setup_coherent_ht_domain();
 187         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
 188
 189 #if 0
 190         print_debug("after ht stuff\n");
 191         print_pci_devices();
 192 #endif
 193
 194         if (needs_reset) {
 195                 print_info("ht reset -\r\n");
 196                 soft_reset();
 197         }
 198
 199 #if 0
 200         print_pci_devices();
 201 #endif
 202
 203         enable_smbus();
 204
 205 #if 0
 206         dump_spd_registers(&cpu[0]);
 207 #endif
 208
 209         memreset_setup();
 210         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 211
 212 #if 0
 213         dump_pci_devices();
 214 #endif
 215
 216 #if 0
 217         dump_pci_device(PCI_DEV(0, 0x18, 2));
 218 #endif
 219
 220 #if 0
 221         /* Check the first 1M */
 222         ram_check(0x00000000, 0x001000000);
 223 #endif
 224 }