4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses COREBOOT_EXTRA_VERSION
41 uses DEFAULT_CONSOLE_LOGLEVEL
42 uses MAXIMUM_CONSOLE_LOGLEVEL
43 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
49 uses CONFIG_CONSOLE_VGA
50 uses CONFIG_PCI_ROM_RUN
55 uses CONFIG_USE_PRINTK_IN_CAR
63 ## ROM_SIZE is the size of boot ROM that this board will use.
65 default ROM_SIZE=524288
68 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
70 default FALLBACK_SIZE=0x40000
73 ## Build code for the fallback boot
75 default HAVE_FALLBACK_BOOT=1
78 ## Build code to reset the motherboard from coreboot
80 default HAVE_HARD_RESET=1
83 ## Build code to export a programmable irq routing table
85 default HAVE_PIRQ_TABLE=1
86 default IRQ_SLOT_COUNT=9
89 ## Build code to export an x86 MP table
90 ## Useful for specifying IRQ routing values
92 default HAVE_MP_TABLE=1
95 ## Build code to export a CMOS option table
97 default HAVE_OPTION_TABLE=1
100 ## Move the default coreboot cmos range off of AMD RTC registers
102 default LB_CKS_RANGE_START=49
103 default LB_CKS_RANGE_END=122
104 default LB_CKS_LOC=123
107 ## Build code for SMP support
108 ## Only worry about 2 micro processors
111 default CONFIG_MAX_CPUS=2
112 default CONFIG_MAX_PHYSICAL_CPUS=2
115 ## Build code to setup a generic IOAPIC
117 default CONFIG_IOAPIC=1
120 default CONFIG_CONSOLE_VGA=1
121 default CONFIG_PCI_ROM_RUN=1
124 ## enable CACHE_AS_RAM specifics
126 default USE_DCACHE_RAM=1
127 default DCACHE_RAM_BASE=0xcf000
128 default DCACHE_RAM_SIZE=0x1000
129 default CONFIG_USE_INIT=0
132 ## Clean up the motherboard id strings
134 default MAINBOARD_PART_NUMBER="E326"
135 default MAINBOARD_VENDOR="IBM"
136 #default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
137 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
140 ### coreboot layout values
143 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
144 default ROM_IMAGE_SIZE = 65536
147 ## Use a small 8K stack
149 default STACK_SIZE=0x2000
152 ## Use a small 16K heap
154 default HEAP_SIZE=0x8000
157 ## Only use the option table in a normal image
159 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
162 ## Coreboot C code runs at this location in RAM
164 default _RAMBASE=0x00004000
167 ## Load the payload from the ROM
169 default CONFIG_ROM_PAYLOAD = 1
172 ### Defaults of options that you may want to override in the target config file
176 ## The default compiler
178 default CC="$(CROSS_COMPILE)gcc -m32"
181 default CONFIG_USE_PRINTK_IN_CAR=1
184 ## The Serial Console
187 # To Enable the Serial Console
188 default CONFIG_CONSOLE_SERIAL8250=1
190 ## Select the serial console baud rate
191 default TTYS0_BAUD=115200
192 #default TTYS0_BAUD=57600
193 #default TTYS0_BAUD=38400
194 #default TTYS0_BAUD=19200
195 #default TTYS0_BAUD=9600
196 #default TTYS0_BAUD=4800
197 #default TTYS0_BAUD=2400
198 #default TTYS0_BAUD=1200
200 # Select the serial console base port
201 default TTYS0_BASE=0x3f8
203 # Select the serial protocol
204 # This defaults to 8 data bits, 1 stop bit, and no parity
205 default TTYS0_LCS=0x3
208 ### Select the coreboot loglevel
210 ## EMERG 1 system is unusable
211 ## ALERT 2 action must be taken immediately
212 ## CRIT 3 critical conditions
213 ## ERR 4 error conditions
214 ## WARNING 5 warning conditions
215 ## NOTICE 6 normal but significant condition
216 ## INFO 7 informational
217 ## DEBUG 8 debug-level messages
218 ## SPEW 9 Way too many details
220 ## Request this level of debugging output
221 default DEFAULT_CONSOLE_LOGLEVEL=8
222 ## At a maximum only compile in this level of debugging
223 default MAXIMUM_CONSOLE_LOGLEVEL=8
226 ## Select power on after power fail setting
227 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
234 default CONFIG_ROMFS=0