3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
29 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
35 uses COREBOOT_EXTRA_VERSION
40 uses DEFAULT_CONSOLE_LOGLEVEL
41 uses MAXIMUM_CONSOLE_LOGLEVEL
42 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
43 uses CONFIG_CONSOLE_SERIAL8250
48 uses CONFIG_CONSOLE_VGA
49 uses CONFIG_PCI_ROM_RUN
54 uses CONFIG_USE_PRINTK_IN_CAR
62 ## ROM_SIZE is the size of boot ROM that this board will use.
64 default ROM_SIZE=524288
67 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
69 default FALLBACK_SIZE=0x40000
72 ## Build code for the fallback boot
74 default HAVE_FALLBACK_BOOT=1
77 ## Build code to reset the motherboard from coreboot
79 default HAVE_HARD_RESET=1
82 ## Build code to export a programmable irq routing table
84 default HAVE_PIRQ_TABLE=1
85 default IRQ_SLOT_COUNT=9
88 ## Build code to export an x86 MP table
89 ## Useful for specifying IRQ routing values
91 default HAVE_MP_TABLE=1
94 ## Build code to export a CMOS option table
96 default HAVE_OPTION_TABLE=1
99 ## Move the default coreboot cmos range off of AMD RTC registers
101 default LB_CKS_RANGE_START=49
102 default LB_CKS_RANGE_END=122
103 default LB_CKS_LOC=123
106 ## Build code for SMP support
107 ## Only worry about 2 micro processors
110 default CONFIG_MAX_CPUS=2
111 default CONFIG_MAX_PHYSICAL_CPUS=2
114 ## Build code to setup a generic IOAPIC
116 default CONFIG_IOAPIC=1
119 default CONFIG_CONSOLE_VGA=1
120 default CONFIG_PCI_ROM_RUN=1
123 ## enable CACHE_AS_RAM specifics
125 default USE_DCACHE_RAM=1
126 default DCACHE_RAM_BASE=0xcf000
127 default DCACHE_RAM_SIZE=0x1000
128 default CONFIG_USE_INIT=0
131 ## Clean up the motherboard id strings
133 default MAINBOARD_PART_NUMBER="E326"
134 default MAINBOARD_VENDOR="IBM"
135 #default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
136 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
139 ### coreboot layout values
142 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
143 default ROM_IMAGE_SIZE = 65536
146 ## Use a small 8K stack
148 default STACK_SIZE=0x2000
151 ## Use a small 16K heap
153 default HEAP_SIZE=0x8000
156 ## Only use the option table in a normal image
158 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
161 ## Coreboot C code runs at this location in RAM
163 default _RAMBASE=0x00004000
166 ## Load the payload from the ROM
168 default CONFIG_ROM_PAYLOAD = 1
171 ### Defaults of options that you may want to override in the target config file
175 ## The default compiler
177 default CC="$(CROSS_COMPILE)gcc -m32"
180 default CONFIG_USE_PRINTK_IN_CAR=1
183 ## The Serial Console
186 # To Enable the Serial Console
187 default CONFIG_CONSOLE_SERIAL8250=1
189 ## Select the serial console baud rate
190 default TTYS0_BAUD=115200
191 #default TTYS0_BAUD=57600
192 #default TTYS0_BAUD=38400
193 #default TTYS0_BAUD=19200
194 #default TTYS0_BAUD=9600
195 #default TTYS0_BAUD=4800
196 #default TTYS0_BAUD=2400
197 #default TTYS0_BAUD=1200
199 # Select the serial console base port
200 default TTYS0_BASE=0x3f8
202 # Select the serial protocol
203 # This defaults to 8 data bits, 1 stop bit, and no parity
204 default TTYS0_LCS=0x3
207 ### Select the coreboot loglevel
209 ## EMERG 1 system is unusable
210 ## ALERT 2 action must be taken immediately
211 ## CRIT 3 critical conditions
212 ## ERR 4 error conditions
213 ## WARNING 5 warning conditions
214 ## NOTICE 6 normal but significant condition
215 ## INFO 7 informational
216 ## DEBUG 8 debug-level messages
217 ## SPEW 9 Way too many details
219 ## Request this level of debugging output
220 default DEFAULT_CONSOLE_LOGLEVEL=8
221 ## At a maximum only compile in this level of debugging
222 default MAXIMUM_CONSOLE_LOGLEVEL=8
225 ## Select power on after power fail setting
226 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"