3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
28 uses LB_CKS_RANGE_START
31 uses MAINBOARD_PART_NUMBER
34 uses LINUXBIOS_EXTRA_VERSION
39 uses DEFAULT_CONSOLE_LOGLEVEL
40 uses MAXIMUM_CONSOLE_LOGLEVEL
41 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
42 uses CONFIG_CONSOLE_SERIAL8250
47 uses CONFIG_CONSOLE_VGA
48 uses CONFIG_PCI_ROM_RUN
60 ## ROM_SIZE is the size of boot ROM that this board will use.
62 default ROM_SIZE=524288
65 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
67 default FALLBACK_SIZE=0x40000
70 ## Build code for the fallback boot
72 default HAVE_FALLBACK_BOOT=1
75 ## Build code to reset the motherboard from linuxBIOS
77 default HAVE_HARD_RESET=1
80 ## Build code to export a programmable irq routing table
82 default HAVE_PIRQ_TABLE=1
83 default IRQ_SLOT_COUNT=9
86 ## Build code to export an x86 MP table
87 ## Useful for specifying IRQ routing values
89 default HAVE_MP_TABLE=1
92 ## Build code to export a CMOS option table
94 default HAVE_OPTION_TABLE=1
97 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
99 default LB_CKS_RANGE_START=49
100 default LB_CKS_RANGE_END=122
101 default LB_CKS_LOC=123
104 ## Build code for SMP support
105 ## Only worry about 2 micro processors
108 default CONFIG_MAX_CPUS=2
109 default CONFIG_MAX_PHYSICAL_CPUS=2
112 ## Build code to setup a generic IOAPIC
114 default CONFIG_IOAPIC=1
117 default CONFIG_CONSOLE_VGA=1
118 default CONFIG_PCI_ROM_RUN=1
121 ## enable CACHE_AS_RAM specifics
123 default USE_DCACHE_RAM=1
124 default DCACHE_RAM_BASE=0xcf000
125 default DCACHE_RAM_SIZE=0x1000
126 default CONFIG_USE_INIT=0
129 ## Clean up the motherboard id strings
131 default MAINBOARD_PART_NUMBER="E326"
132 default MAINBOARD_VENDOR="IBM"
133 #default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
134 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
137 ### LinuxBIOS layout values
140 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
141 default ROM_IMAGE_SIZE = 65536
144 ## Use a small 8K stack
146 default STACK_SIZE=0x2000
149 ## Use a small 16K heap
151 default HEAP_SIZE=0x8000
154 ## Only use the option table in a normal image
156 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
159 ## LinuxBIOS C code runs at this location in RAM
161 default _RAMBASE=0x00004000
164 ## Load the payload from the ROM
166 default CONFIG_ROM_PAYLOAD = 1
169 ### Defaults of options that you may want to override in the target config file
173 ## The default compiler
175 default CC="$(CROSS_COMPILE)gcc -m32"
179 ## The Serial Console
182 # To Enable the Serial Console
183 default CONFIG_CONSOLE_SERIAL8250=1
185 ## Select the serial console baud rate
186 default TTYS0_BAUD=115200
187 #default TTYS0_BAUD=57600
188 #default TTYS0_BAUD=38400
189 #default TTYS0_BAUD=19200
190 #default TTYS0_BAUD=9600
191 #default TTYS0_BAUD=4800
192 #default TTYS0_BAUD=2400
193 #default TTYS0_BAUD=1200
195 # Select the serial console base port
196 default TTYS0_BASE=0x3f8
198 # Select the serial protocol
199 # This defaults to 8 data bits, 1 stop bit, and no parity
200 default TTYS0_LCS=0x3
203 ### Select the linuxBIOS loglevel
205 ## EMERG 1 system is unusable
206 ## ALERT 2 action must be taken immediately
207 ## CRIT 3 critical conditions
208 ## ERR 4 error conditions
209 ## WARNING 5 warning conditions
210 ## NOTICE 6 normal but significant condition
211 ## INFO 7 informational
212 ## DEBUG 8 debug-level messages
213 ## SPEW 9 Way too many details
215 ## Request this level of debugging output
216 default DEFAULT_CONSOLE_LOGLEVEL=8
217 ## At a maximum only compile in this level of debugging
218 default MAXIMUM_CONSOLE_LOGLEVEL=8
221 ## Select power on after power fail setting
222 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"