3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_STREAM
19 uses CONFIG_ROM_STREAM_START
27 uses LB_CKS_RANGE_START
30 uses MAINBOARD_PART_NUMBER
33 uses LINUXBIOS_EXTRA_VERSION
38 uses DEFAULT_CONSOLE_LOGLEVEL
39 uses MAXIMUM_CONSOLE_LOGLEVEL
40 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 uses CONFIG_CONSOLE_SERIAL8250
46 uses CONFIG_CONSOLE_VGA
47 uses CONFIG_PCI_ROM_RUN
57 ## ROM_SIZE is the size of boot ROM that this board will use.
59 default ROM_SIZE=524288
62 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
64 default FALLBACK_SIZE=131072
67 ## Build code for the fallback boot
69 default HAVE_FALLBACK_BOOT=1
72 ## Build code to reset the motherboard from linuxBIOS
74 default HAVE_HARD_RESET=1
77 ## Build code to export a programmable irq routing table
79 default HAVE_PIRQ_TABLE=1
80 default IRQ_SLOT_COUNT=9
83 ## Build code to export an x86 MP table
84 ## Useful for specifying IRQ routing values
86 default HAVE_MP_TABLE=1
89 ## Build code to export a CMOS option table
91 default HAVE_OPTION_TABLE=1
94 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
96 default LB_CKS_RANGE_START=49
97 default LB_CKS_RANGE_END=122
98 default LB_CKS_LOC=123
101 ## Build code for SMP support
102 ## Only worry about 2 micro processors
105 default CONFIG_MAX_CPUS=2
106 default CONFIG_MAX_PHYSICAL_CPUS=2
109 ## Build code to setup a generic IOAPIC
111 default CONFIG_IOAPIC=1
114 default CONFIG_CONSOLE_VGA=1
115 default CONFIG_PCI_ROM_RUN=1
118 ## Clean up the motherboard id strings
120 default MAINBOARD_PART_NUMBER="E326"
121 default MAINBOARD_VENDOR="IBM"
122 #default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
123 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
126 ### LinuxBIOS layout values
129 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
130 default ROM_IMAGE_SIZE = 65536
133 ## Use a small 8K stack
135 default STACK_SIZE=0x2000
138 ## Use a small 16K heap
140 default HEAP_SIZE=0x8000
143 ## Only use the option table in a normal image
145 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
148 ## LinuxBIOS C code runs at this location in RAM
150 default _RAMBASE=0x00004000
153 ## Load the payload from the ROM
155 default CONFIG_ROM_STREAM = 1
158 ### Defaults of options that you may want to override in the target config file
162 ## The default compiler
164 default CC="$(CROSS_COMPILE)gcc -m32"
168 ## The Serial Console
171 # To Enable the Serial Console
172 default CONFIG_CONSOLE_SERIAL8250=1
174 ## Select the serial console baud rate
175 default TTYS0_BAUD=115200
176 #default TTYS0_BAUD=57600
177 #default TTYS0_BAUD=38400
178 #default TTYS0_BAUD=19200
179 #default TTYS0_BAUD=9600
180 #default TTYS0_BAUD=4800
181 #default TTYS0_BAUD=2400
182 #default TTYS0_BAUD=1200
184 # Select the serial console base port
185 default TTYS0_BASE=0x3f8
187 # Select the serial protocol
188 # This defaults to 8 data bits, 1 stop bit, and no parity
189 default TTYS0_LCS=0x3
192 ### Select the linuxBIOS loglevel
194 ## EMERG 1 system is unusable
195 ## ALERT 2 action must be taken immediately
196 ## CRIT 3 critical conditions
197 ## ERR 4 error conditions
198 ## WARNING 5 warning conditions
199 ## NOTICE 6 normal but significant condition
200 ## INFO 7 informational
201 ## DEBUG 8 debug-level messages
202 ## SPEW 9 Way too many details
204 ## Request this level of debugging output
205 default DEFAULT_CONSOLE_LOGLEVEL=8
206 ## At a maximum only compile in this level of debugging
207 default MAXIMUM_CONSOLE_LOGLEVEL=8
210 ## Select power on after power fail setting
211 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"