2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_MP_TABLE object mptable.o end
47 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/failover.c ./romcc"
55 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
58 makerule ./failover.inc
59 depends "$(MAINBOARD)/failover.c ./romcc"
60 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
64 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
65 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
68 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
69 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
73 ## Build our 16 bit and 32 bit linuxBIOS entry code
75 mainboardinit cpu/x86/16bit/entry16.inc
76 mainboardinit cpu/x86/32bit/entry32.inc
77 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
81 ## Build our reset vector (This is where linuxBIOS is entered)
84 mainboardinit cpu/x86/16bit/reset16.inc
85 ldscript /cpu/x86/16bit/reset16.lds
87 mainboardinit cpu/x86/32bit/reset32.inc
88 ldscript /cpu/x86/32bit/reset32.lds
91 ### Should this be in the northbridge code?
92 mainboardinit arch/i386/lib/cpu_reset.inc
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
101 ### This is the early phase of linuxBIOS startup
102 ### Things are delicate and we test to see if we should
103 ### failover to another image.
105 if USE_FALLBACK_IMAGE
106 ldscript /arch/i386/lib/failover.lds
107 mainboardinit ./failover.inc
111 ### O.k. We aren't just an intermediary anymore!
117 mainboardinit cpu/x86/fpu/enable_fpu.inc
118 mainboardinit cpu/x86/mmx/enable_mmx.inc
119 mainboardinit cpu/x86/sse/enable_sse.inc
120 mainboardinit ./auto.inc
121 mainboardinit cpu/x86/sse/disable_sse.inc
122 mainboardinit cpu/x86/mmx/disable_mmx.inc
125 ## Include the secondary Configuration files
131 chip northbridge/amd/amdk8/root_complex
132 device apic_cluster 0 on
133 chip cpu/amd/socket_940
138 device pci_domain 0 on
139 chip northbridge/amd/amdk8
140 device pci 18.0 on end # LDT 0
141 device pci 18.0 on # LDT 1
142 chip southbridge/amd/amd8131
143 device pci 0.0 on end
144 device pci 0.1 on end
145 device pci 1.0 on end
146 device pci 1.1 on end
148 chip southbridge/amd/amd8111
150 device pci 0.0 on end
151 device pci 0.1 on end
152 device pci 0.2 on end
153 device pci 1.0 off end
154 chip drivers/pci/onboard
155 device pci 5.0 on end # ATI Rage XL
156 register "rom_address" = "0xfff80000"
160 chip superio/nsc/pc87366
161 device pnp 2e.0 off # Floppy
166 device pnp 2e.1 off # Parallel Port
170 device pnp 2e.2 off # Com 2
174 device pnp 2e.3 on # Com 1
178 device pnp 2e.4 off end # SWC
179 device pnp 2e.5 off end # Mouse
180 device pnp 2e.6 on # Keyboard
185 device pnp 2e.7 off end # GPIO
186 device pnp 2e.8 off end # ACB
187 device pnp 2e.9 off end # FSCM
188 device pnp 2e.a off end # WDT
191 device pci 1.1 on end
192 device pci 1.2 on end
193 device pci 1.3 on end
194 device pci 1.5 off end
195 device pci 1.6 off end
196 register "ide0_enable" = "1"
197 register "ide1_enable" = "1"
199 end # device pci 18.0
200 device pci 18.0 on end # LDT2
201 device pci 18.1 on end
202 device pci 18.2 on end
203 device pci 18.3 on end