src/mainboard/ibm/e326/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 ##
  51 ## Romcc output
  52 ##
  53 makerule ./failover.E
  54         depends "$(MAINBOARD)/failover.c ./romcc"
  55         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  56 end
  57
  58 makerule ./failover.inc
  59         depends "$(MAINBOARD)/failover.c ./romcc"
  60         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  61 end
  62
  63 makerule ./auto.E
  64         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  65         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  66 end
  67 makerule ./auto.inc
  68         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  69         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  70 end
  71
  72 ##
  73 ## Build our 16 bit and 32 bit linuxBIOS entry code
  74 ##
  75 mainboardinit cpu/x86/16bit/entry16.inc
  76 mainboardinit cpu/x86/32bit/entry32.inc
  77 ldscript /cpu/x86/16bit/entry16.lds
  78 ldscript /cpu/x86/32bit/entry32.lds
  79
  80 ##
  81 ## Build our reset vector (This is where linuxBIOS is entered)
  82 ##
  83 if USE_FALLBACK_IMAGE
  84         mainboardinit cpu/x86/16bit/reset16.inc
  85         ldscript /cpu/x86/16bit/reset16.lds
  86 else
  87         mainboardinit cpu/x86/32bit/reset32.inc
  88         ldscript /cpu/x86/32bit/reset32.lds
  89 end
  90
  91 ### Should this be in the northbridge code?
  92 mainboardinit arch/i386/lib/cpu_reset.inc
  93
  94 ##
  95 ## Include an id string (For safe flashing)
  96 ##
  97 mainboardinit arch/i386/lib/id.inc
  98 ldscript /arch/i386/lib/id.lds
  99
 100 ###
 101 ### This is the early phase of linuxBIOS startup
 102 ### Things are delicate and we test to see if we should
 103 ### failover to another image.
 104 ###
 105 if USE_FALLBACK_IMAGE
 106         ldscript /arch/i386/lib/failover.lds
 107         mainboardinit ./failover.inc
 108 end
 109
 110 ###
 111 ### O.k. We aren't just an intermediary anymore!
 112 ###
 113
 114 ##
 115 ## Setup RAM
 116 ##
 117 mainboardinit cpu/x86/fpu/enable_fpu.inc
 118 mainboardinit cpu/x86/mmx/enable_mmx.inc
 119 mainboardinit cpu/x86/sse/enable_sse.inc
 120 mainboardinit ./auto.inc
 121 mainboardinit cpu/x86/sse/disable_sse.inc
 122 mainboardinit cpu/x86/mmx/disable_mmx.inc
 123
 124 ##
 125 ## Include the secondary Configuration files
 126 ##
 127 dir /pc80
 128 config chip.h
 129
 130
 131 chip northbridge/amd/amdk8/root_complex
 132         device apic_cluster 0 on
 133                 chip cpu/amd/socket_940
 134                         device apic 0 on end
 135                 end
 136         end
 137
 138         device pci_domain 0 on
 139                 chip northbridge/amd/amdk8
 140                         device pci 18.0 on end # LDT 0
 141                         device pci 18.0 on     # LDT 1
 142                                 chip southbridge/amd/amd8131
 143                                         device pci 0.0 on end
 144                                         device pci 0.1 on end
 145                                         device pci 1.0 on end
 146                                         device pci 1.1 on end
 147                                 end
 148                                 chip southbridge/amd/amd8111
 149                                         device pci 0.0 on
 150                                                 device pci 0.0 on end
 151                                                 device pci 0.1 on end
 152                                                 device pci 0.2 on end
 153                                                 device pci 1.0 off end
 154                                                 chip drivers/pci/onboard
 155                                                         device pci 5.0 on end # ATI Rage XL
 156                                                         register "rom_address" = "0xfff80000"
 157                                                 end
 158                                         end
 159                                         device pci 1.0 on
 160                                                 chip superio/NSC/pc87366
 161                                                         device  pnp 2e.0 off  # Floppy
 162                                                                  io 0x60 = 0x3f0
 163                                                                 irq 0x70 = 6
 164                                                                 drq 0x74 = 2
 165                                                         end
 166                                                         device pnp 2e.1 off  # Parallel Port
 167                                                                  io 0x60 = 0x378
 168                                                                 irq 0x70 = 7
 169                                                         end
 170                                                         device pnp 2e.2 off # Com 2
 171                                                                  io 0x60 = 0x2f8
 172                                                                 irq 0x70 = 3
 173                                                         end
 174                                                         device pnp 2e.3 on  # Com 1
 175                                                                  io 0x60 = 0x3f8
 176                                                                 irq 0x70 = 4
 177                                                         end
 178                                                         device pnp 2e.4 off end # SWC
 179                                                         device pnp 2e.5 off end # Mouse
 180                                                         device pnp 2e.6 on  # Keyboard
 181                                                                  io 0x60 = 0x60
 182                                                                  io 0x62 = 0x64
 183                                                                 irq 0x70 = 1
 184                                                         end
 185                                                         device pnp 2e.7 off end # GPIO
 186                                                         device pnp 2e.8 off end # ACB
 187                                                         device pnp 2e.9 off end # FSCM
 188                                                         device pnp 2e.a off end # WDT
 189                                                 end
 190                                         end
 191                                         device pci 1.1 on end
 192                                         device pci 1.2 on end
 193                                         device pci 1.3 on end
 194                                         device pci 1.5 off end
 195                                         device pci 1.6 off end
 196                                         register "ide0_enable" = "1"
 197                                         register "ide1_enable" = "1"
 198                                 end
 199                         end #  device pci 18.0
 200                         device pci 18.0 on end # LDT2
 201                         device pci 18.1 on end
 202                         device pci 18.2 on end
 203                         device pci 18.3 on end
 204                 end
 205         end
 206 end
 207