3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
10 #include <cpu/amd/model_fxx_rev.h>
11 #include "northbridge/amd/amdk8/incoherent_ht.c"
12 #include "southbridge/amd/amd8111/early_smbus.c"
13 #include "northbridge/amd/amdk8/raminit.h"
14 #include "cpu/amd/model_fxx/apic_timer.c"
15 #include "lib/delay.c"
16 #include "northbridge/amd/amdk8/reset_test.c"
17 #include "northbridge/amd/amdk8/debug.c"
18 #include "superio/nsc/pc87366/early_serial.c"
19 #include "cpu/x86/mtrr/earlymtrr.c"
20 #include "cpu/x86/bist.h"
21 #include "northbridge/amd/amdk8/setup_resource_map.c"
23 #include "southbridge/amd/amd8111/early_ctrl.c"
25 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
27 static void memreset_setup(void)
29 if (is_cpu_pre_c0()) {
30 /* Set the memreset low. */
31 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
32 /* Ensure the BIOS has control of the memory lines. */
33 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
35 /* Ensure the CPU has control of the memory lines. */
36 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
40 static void memreset(int controllers, const struct mem_controller *ctrl)
42 if (is_cpu_pre_c0()) {
44 /* Set memreset high. */
45 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
50 static void activate_spd_rom(const struct mem_controller *ctrl) { }
52 static inline int spd_read_byte(unsigned device, unsigned address)
54 return smbus_read_byte(device, address);
57 #include "northbridge/amd/amdk8/raminit.c"
58 #include "resourcemap.c"
59 #include "northbridge/amd/amdk8/coherent_ht.c"
60 #include "lib/generic_sdram.c"
61 #include "cpu/amd/dualcore/dualcore.c"
62 #include "cpu/amd/car/post_cache_as_ram.c"
63 #include "cpu/amd/model_fxx/init_cpus.c"
65 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
67 static const struct mem_controller cpu[] = {
70 .f0 = PCI_DEV(0, 0x18, 0),
71 .f1 = PCI_DEV(0, 0x18, 1),
72 .f2 = PCI_DEV(0, 0x18, 2),
73 .f3 = PCI_DEV(0, 0x18, 3),
74 .channel0 = { DIMM0, DIMM2, 0, 0 },
75 .channel1 = { DIMM1, DIMM3, 0, 0 },
77 #if CONFIG_MAX_PHYSICAL_CPUS > 1
80 .f0 = PCI_DEV(0, 0x19, 0),
81 .f1 = PCI_DEV(0, 0x19, 1),
82 .f2 = PCI_DEV(0, 0x19, 2),
83 .f3 = PCI_DEV(0, 0x19, 3),
84 .channel0 = { DIMM4, DIMM6, 0, 0 },
85 .channel1 = { DIMM5, DIMM7, 0, 0 },
93 init_cpus(cpu_init_detectedx);
95 pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
98 /* Halt if there was a built in self test failure */
99 report_bist_failure(bist);
101 setup_ibm_e325_resource_map();
103 needs_reset = setup_coherent_ht_domain();
105 #if CONFIG_LOGICAL_CPUS==1
106 // It is said that we should start core1 after all core0 launched
109 // automatically set that for you, but you might meet tight space
110 needs_reset |= ht_setup_chains_x();
113 print_info("ht reset -\n");
120 sdram_initialize(ARRAY_SIZE(cpu), cpu);