src/mainboard/ibm/e325/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17
  18 #include <cpu/amd/model_fxx_rev.h>
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  29
  30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  36
  37 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  38
  39 static void memreset_setup(void)
  40 {
  41         if (is_cpu_pre_c0()) {
  42                 /* Set the memreset low */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  44                 /* Ensure the BIOS has control of the memory lines */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46         } else {
  47                 /* Ensure the CPU has controll of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  49         }
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54         if (is_cpu_pre_c0()) {
  55                 udelay(800);
  56                 /* Set memreset_high */
  57                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  58                 udelay(90);
  59         }
  60 }
  61
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65         /* nothing to do */
  66 }
  67
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #define QRANK_DIMM_SUPPORT 1
  74
  75 #include "northbridge/amd/amdk8/raminit.c"
  76 #include "resourcemap.c"
  77 #include "northbridge/amd/amdk8/coherent_ht.c"
  78 #include "lib/generic_sdram.c"
  79
  80 #if CONFIG_LOGICAL_CPUS==1
  81 #define SET_NB_CFG_54 1
  82 #endif
  83 #include "cpu/amd/dualcore/dualcore.c"
  84
  85 #define FIRST_CPU  1
  86 #define SECOND_CPU 1
  87 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  88
  89 #include "cpu/amd/car/copy_and_run.c"
  90
  91 #include "cpu/amd/car/post_cache_as_ram.c"
  92
  93 #include "cpu/amd/model_fxx/init_cpus.c"
  94
  95
  96 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  97 #include "northbridge/amd/amdk8/early_ht.c"
  98
  99 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 100 {
 101         static const struct mem_controller cpu[] = {
 102                 {
 103                         .node_id = 0,
 104                         .f0 = PCI_DEV(0, 0x18, 0),
 105                         .f1 = PCI_DEV(0, 0x18, 1),
 106                         .f2 = PCI_DEV(0, 0x18, 2),
 107                         .f3 = PCI_DEV(0, 0x18, 3),
 108                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 109                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 110                 },
 111 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 112                 {
 113                         .node_id = 1,
 114                         .f0 = PCI_DEV(0, 0x19, 0),
 115                         .f1 = PCI_DEV(0, 0x19, 1),
 116                         .f2 = PCI_DEV(0, 0x19, 2),
 117                         .f3 = PCI_DEV(0, 0x19, 3),
 118                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 119                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 120                 },
 121 #endif
 122         };
 123
 124         int needs_reset;
 125
 126         if (!cpu_init_detectedx && boot_cpu()) {
 127                 /* Nothing special needs to be done to find bus 0 */
 128                 /* Allow the HT devices to be found */
 129
 130                 enumerate_ht_chain();
 131
 132                 amd8111_enable_rom();
 133         }
 134
 135         if (bist == 0) {
 136                 init_cpus(cpu_init_detectedx);
 137         }
 138
 139         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 140         uart_init();
 141         console_init();
 142
 143         /* Halt if there was a built in self test failure */
 144         report_bist_failure(bist);
 145
 146         setup_ibm_e325_resource_map();
 147
 148         needs_reset = setup_coherent_ht_domain();
 149
 150 #if CONFIG_LOGICAL_CPUS==1
 151         // It is said that we should start core1 after all core0 launched
 152         start_other_cores();
 153 #endif
 154         // automatically set that for you, but you might meet tight space
 155         needs_reset |= ht_setup_chains_x();
 156
 157         if (needs_reset) {
 158                 print_info("ht reset -\r\n");
 159                 soft_reset();
 160         }
 161
 162         enable_smbus();
 163
 164         memreset_setup();
 165         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 166
 167         post_cache_as_ram();
 168
 169 }