6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
12 #include "option_table.h"
13 #include "pc80/mc146818rtc_early.c"
14 #include "pc80/serial.c"
15 #include "arch/i386/lib/console.c"
16 #include "lib/ramtest.c"
18 #include <cpu/amd/model_fxx_rev.h>
19 #include "northbridge/amd/amdk8/incoherent_ht.c"
20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
21 #include "northbridge/amd/amdk8/raminit.h"
22 #include "cpu/amd/model_fxx/apic_timer.c"
23 #include "lib/delay.c"
25 #include "cpu/x86/lapic/boot_cpu.c"
26 #include "northbridge/amd/amdk8/reset_test.c"
27 #include "northbridge/amd/amdk8/debug.c"
28 #include "superio/nsc/pc87366/pc87366_early_serial.c"
30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
31 #include "cpu/x86/bist.h"
33 #include "northbridge/amd/amdk8/setup_resource_map.c"
35 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
37 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
39 static void memreset_setup(void)
41 if (is_cpu_pre_c0()) {
42 /* Set the memreset low */
43 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
44 /* Ensure the BIOS has control of the memory lines */
45 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
47 /* Ensure the CPU has controll of the memory lines */
48 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
52 static void memreset(int controllers, const struct mem_controller *ctrl)
54 if (is_cpu_pre_c0()) {
56 /* Set memreset_high */
57 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
68 static inline int spd_read_byte(unsigned device, unsigned address)
70 return smbus_read_byte(device, address);
73 #define QRANK_DIMM_SUPPORT 1
75 #include "northbridge/amd/amdk8/raminit.c"
76 #include "resourcemap.c"
77 #include "northbridge/amd/amdk8/coherent_ht.c"
78 #include "lib/generic_sdram.c"
80 #if CONFIG_LOGICAL_CPUS==1
81 #define SET_NB_CFG_54 1
83 #include "cpu/amd/dualcore/dualcore.c"
87 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
89 #include "cpu/amd/car/copy_and_run.c"
91 #include "cpu/amd/car/post_cache_as_ram.c"
93 #include "cpu/amd/model_fxx/init_cpus.c"
96 #if CONFIG_USE_FALLBACK_IMAGE == 1
98 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
99 #include "northbridge/amd/amdk8/early_ht.c"
101 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
103 unsigned last_boot_normal_x = last_boot_normal();
105 /* Is this a cpu only reset? or Is this a secondary cpu? */
106 if ((cpu_init_detectedx) || (!boot_cpu())) {
107 if (last_boot_normal_x) {
114 /* Nothing special needs to be done to find bus 0 */
115 /* Allow the HT devices to be found */
117 enumerate_ht_chain();
119 amd8111_enable_rom();
121 /* Is this a deliberate reset by the bios */
122 if (bios_reset_detected() && last_boot_normal_x) {
125 /* This is the primary cpu how should I boot? */
126 else if (do_normal_boot()) {
133 __asm__ volatile ("jmp __normal_image"
135 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
143 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
145 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
148 #if CONFIG_USE_FALLBACK_IMAGE == 1
149 failover_process(bist, cpu_init_detectedx);
151 real_main(bist, cpu_init_detectedx);
155 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
157 static const struct mem_controller cpu[] = {
160 .f0 = PCI_DEV(0, 0x18, 0),
161 .f1 = PCI_DEV(0, 0x18, 1),
162 .f2 = PCI_DEV(0, 0x18, 2),
163 .f3 = PCI_DEV(0, 0x18, 3),
164 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
165 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
167 #if CONFIG_MAX_PHYSICAL_CPUS > 1
170 .f0 = PCI_DEV(0, 0x19, 0),
171 .f1 = PCI_DEV(0, 0x19, 1),
172 .f2 = PCI_DEV(0, 0x19, 2),
173 .f3 = PCI_DEV(0, 0x19, 3),
174 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
175 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
183 init_cpus(cpu_init_detectedx);
186 pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
190 /* Halt if there was a built in self test failure */
191 report_bist_failure(bist);
193 setup_ibm_e325_resource_map();
195 needs_reset = setup_coherent_ht_domain();
197 #if CONFIG_LOGICAL_CPUS==1
198 // It is said that we should start core1 after all core0 launched
201 // automatically set that for you, but you might meet tight space
202 needs_reset |= ht_setup_chains_x();
205 print_info("ht reset -\r\n");
212 sdram_initialize(ARRAY_SIZE(cpu), cpu);