1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 struct mp_config_table *mc;
12 unsigned char bus_num;
13 unsigned char bus_isa;
14 unsigned char bus_8111_0;
15 unsigned char bus_8111_1;
16 unsigned char bus_8131_1;
17 unsigned char bus_8131_2;
19 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
21 mptable_init(mc, "E325 ", LAPIC_ADDR);
23 smp_write_processors(mc);
29 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
31 bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
32 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
33 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
36 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
43 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
45 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
48 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
53 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
55 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
57 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
62 /* define bus and isa numbers */
63 for (bus_num = 0; bus_num < bus_isa; bus_num++) {
64 smp_write_bus(mc, bus_num, "PCI ");
66 smp_write_bus(mc, bus_isa, "ISA ");
68 /* Legacy IOAPIC #2 */
69 smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
74 dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
76 res = find_resource(dev, PCI_BASE_ADDRESS_0);
78 smp_write_ioapic(mc, 0x03, 0x11, res->base);
82 dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
84 res = find_resource(dev, PCI_BASE_ADDRESS_0);
86 smp_write_ioapic(mc, 0x04, 0x11, res->base);
91 mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
93 /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
94 /* Integrated SMBus 2.0 */
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
96 /* Integrated AMD AC97 Audio */
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
99 /* Integrated AMD USB */
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
102 /* On board ATI Rage XL */
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
105 /* On board Broadcom nics */
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
109 /* On board LSI SCSI */
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
112 /* PCI Slot 1 PCIX */
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
118 /* PCI Slot 2 PCIX */
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
124 /* Standard local interrupt assignments:
125 * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
126 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
127 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
129 /* There is no extension information... */
131 /* Compute the checksums */
132 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
133 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
134 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
135 mc, smp_next_mpe_entry(mc));
136 return smp_next_mpe_entry(mc);
139 unsigned long write_smp_table(unsigned long addr)
142 v = smp_write_floating_table(addr);
143 return (unsigned long)smp_write_config_table(v);