src/mainboard/ibm/e325/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17
  18 #include <cpu/amd/model_fxx_rev.h>
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  29
  30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  36
  37 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  38
  39 static void memreset_setup(void)
  40 {
  41         if (is_cpu_pre_c0()) {
  42                 /* Set the memreset low */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  44                 /* Ensure the BIOS has control of the memory lines */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46         } else {
  47                 /* Ensure the CPU has controll of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  49         }
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54         if (is_cpu_pre_c0()) {
  55                 udelay(800);
  56                 /* Set memreset_high */
  57                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  58                 udelay(90);
  59         }
  60 }
  61
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65         /* nothing to do */
  66 }
  67
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #define QRANK_DIMM_SUPPORT 1
  74
  75 #include "northbridge/amd/amdk8/raminit.c"
  76 #include "resourcemap.c"
  77 #include "northbridge/amd/amdk8/coherent_ht.c"
  78 #include "lib/generic_sdram.c"
  79
  80 #if CONFIG_LOGICAL_CPUS==1
  81 #define SET_NB_CFG_54 1
  82 #endif
  83 #include "cpu/amd/dualcore/dualcore.c"
  84
  85 #define FIRST_CPU  1
  86 #define SECOND_CPU 1
  87 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  88
  89 #include "cpu/amd/car/copy_and_run.c"
  90
  91 #include "cpu/amd/car/post_cache_as_ram.c"
  92
  93 #include "cpu/amd/model_fxx/init_cpus.c"
  94
  95
  96 #if CONFIG_USE_FALLBACK_IMAGE == 1
  97
  98 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  99 #include "northbridge/amd/amdk8/early_ht.c"
 100
 101 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 102 {
 103         unsigned last_boot_normal_x = last_boot_normal();
 104
 105         /* Is this a cpu only reset? or Is this a secondary cpu? */
 106         if ((cpu_init_detectedx) || (!boot_cpu())) {
 107                 if (last_boot_normal_x) {
 108                         goto normal_image;
 109                 } else {
 110                         goto fallback_image;
 111                 }
 112         }
 113
 114         /* Nothing special needs to be done to find bus 0 */
 115         /* Allow the HT devices to be found */
 116
 117         enumerate_ht_chain();
 118
 119         amd8111_enable_rom();
 120
 121         /* Is this a deliberate reset by the bios */
 122         if (bios_reset_detected() && last_boot_normal_x) {
 123                 goto normal_image;
 124         }
 125         /* This is the primary cpu how should I boot? */
 126         else if (do_normal_boot()) {
 127                 goto normal_image;
 128         }
 129         else {
 130                 goto fallback_image;
 131         }
 132  normal_image:
 133         __asm__ volatile ("jmp __normal_image"
 134                 : /* outputs */
 135                 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
 136                 );
 137
 138  fallback_image:
 139         ;
 140 }
 141 #endif
 142
 143 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 144
 145 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 146 {
 147
 148 #if CONFIG_USE_FALLBACK_IMAGE == 1
 149         failover_process(bist, cpu_init_detectedx);
 150 #endif
 151         real_main(bist, cpu_init_detectedx);
 152
 153 }
 154
 155 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 156 {
 157         static const struct mem_controller cpu[] = {
 158                 {
 159                         .node_id = 0,
 160                         .f0 = PCI_DEV(0, 0x18, 0),
 161                         .f1 = PCI_DEV(0, 0x18, 1),
 162                         .f2 = PCI_DEV(0, 0x18, 2),
 163                         .f3 = PCI_DEV(0, 0x18, 3),
 164                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 165                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 166                 },
 167 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 168                 {
 169                         .node_id = 1,
 170                         .f0 = PCI_DEV(0, 0x19, 0),
 171                         .f1 = PCI_DEV(0, 0x19, 1),
 172                         .f2 = PCI_DEV(0, 0x19, 2),
 173                         .f3 = PCI_DEV(0, 0x19, 3),
 174                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 175                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 176                 },
 177 #endif
 178         };
 179
 180         int needs_reset;
 181
 182         if (bist == 0) {
 183                 init_cpus(cpu_init_detectedx);
 184         }
 185
 186         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 187         uart_init();
 188         console_init();
 189
 190         /* Halt if there was a built in self test failure */
 191         report_bist_failure(bist);
 192
 193         setup_ibm_e325_resource_map();
 194
 195         needs_reset = setup_coherent_ht_domain();
 196
 197 #if CONFIG_LOGICAL_CPUS==1
 198         // It is said that we should start core1 after all core0 launched
 199         start_other_cores();
 200 #endif
 201         // automatically set that for you, but you might meet tight space
 202         needs_reset |= ht_setup_chains_x();
 203
 204         if (needs_reset) {
 205                 print_info("ht reset -\r\n");
 206                 soft_reset();
 207         }
 208
 209         enable_smbus();
 210
 211         memreset_setup();
 212         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 213
 214         post_cache_as_ram();
 215
 216 }