src/mainboard/ibm/e325/auto.c

   1 #define ASSEMBLY 1
   2 #define DEFAULT_CONSOLE_LOGLEVEL 8
   3 #define MAXIMUM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <arch/cpu.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include <cpu/amd/model_fxx_rev.h>
  24 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void memreset_setup(void)
  47 {
  48         if (is_cpu_pre_c0()) {
  49                 /* Set the memreset low */
  50                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  51                 /* Ensure the BIOS has control of the memory lines */
  52                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  53         } else {
  54                 /* Ensure the CPU has controll of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  56         }
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61         if (is_cpu_pre_c0()) {
  62                 udelay(800);
  63                 /* Set memreset_high */
  64                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  65                 udelay(90);
  66         }
  67 }
  68
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71         /* nothing to do */
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/raminit.c"
  80
  81 #include "northbridge/amd/amdk8/coherent_ht.c"
  82 #include "northbridge/amd/amdk8/incoherent_ht.c"
  83 #include "sdram/generic_sdram.c"
  84 #include "mainboard/ibm/e325/resourcemap.c"
  85 #include "cpu/amd/dualcore/dualcore.c"
  86
  87 #define FIRST_CPU  1
  88 #define SECOND_CPU 1
  89 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  90 static void main(unsigned long bist)
  91 {
  92         static const struct mem_controller cpu[] = {
  93 #if FIRST_CPU
  94                 {
  95                         .node_id = 0,
  96                         .f0 = PCI_DEV(0, 0x18, 0),
  97                         .f1 = PCI_DEV(0, 0x18, 1),
  98                         .f2 = PCI_DEV(0, 0x18, 2),
  99                         .f3 = PCI_DEV(0, 0x18, 3),
 100                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 101                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 102                 },
 103 #endif
 104 #if SECOND_CPU
 105                 {
 106                         .node_id = 1,
 107                         .f0 = PCI_DEV(0, 0x19, 0),
 108                         .f1 = PCI_DEV(0, 0x19, 1),
 109                         .f2 = PCI_DEV(0, 0x19, 2),
 110                         .f3 = PCI_DEV(0, 0x19, 3),
 111                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 112                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 113                 },
 114 #endif
 115         };
 116
 117         int needs_reset;
 118         unsigned nodeid;
 119
 120         if (bist == 0) {
 121                 k8_init_and_stop_secondaries();
 122         }
 123         /* Setup the console */
 124         pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
 125         uart_init();
 126         console_init();
 127
 128         /* Halt if there was a built in self test failure */
 129         report_bist_failure(bist);
 130
 131 #if 0
 132         print_pci_devices();
 133 #endif
 134
 135         setup_ibm_e325_resource_map();
 136
 137 #if 0
 138         print_debug("after setting resource\n");
 139         print_pci_devices();
 140 #endif
 141
 142         needs_reset = setup_coherent_ht_domain();
 143         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
 144
 145 #if 0
 146         print_debug("after ht stuff\n");
 147         print_pci_devices();
 148 #endif
 149
 150         if (needs_reset) {
 151                 print_info("ht reset -\r\n");
 152                 soft_reset();
 153         }
 154
 155 #if 0
 156         print_pci_devices();
 157 #endif
 158
 159         enable_smbus();
 160
 161 #if 0
 162         dump_spd_registers(&cpu[0]);
 163 #endif
 164
 165         memreset_setup();
 166         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 167
 168 #if 0
 169         dump_pci_devices();
 170 #endif
 171
 172 #if 0
 173         dump_pci_device(PCI_DEV(0, 0x18, 2));
 174 #endif
 175
 176 #if 0
 177         /* Check the first 1M */
 178         ram_check(0x00000000, 0x001000000);
 179 #endif
 180 }