src/mainboard/ibm/e325/auto.c

   1 #define ASSEMBLY 1
   2 #define DEFAULT_CONSOLE_LOGLEVEL 8
   3 #define MAXIMUM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <arch/smp/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/k8/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/p6/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/NSC/pc87366/pc87366_early_serial.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  27
  28 static void hard_reset(void)
  29 {
  30         set_bios_reset();
  31
  32         /* enable cf9 */
  33         pci_write_config8(PCI_DEV(1, 0x04, 3), 0x41, 0xf1);
  34         /* reset */
  35         outb(0x0e, 0x0cf9);
  36 }
  37
  38 static void soft_reset(void)
  39 {
  40         set_bios_reset();
  41         pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
  42 }
  43
  44 static void memreset_setup(void)
  45 {
  46         if (is_cpu_pre_c0()) {
  47                 /* Set the memreset low */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  49                 /* Ensure the BIOS has control of the memory lines */
  50                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  51         } else {
  52                 /* Ensure the CPU has controll of the memory lines */
  53                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  54         }
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59         if (is_cpu_pre_c0()) {
  60                 udelay(800);
  61                 /* Set memreset_high */
  62                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  63                 udelay(90);
  64         }
  65 }
  66
  67 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  68 {
  69         /* Routing Table Node i
  70          *
  71          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  72          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  73          *
  74          * [ 0: 3] Request Route
  75          *     [0] Route to this node
  76          *     [1] Route to Link 0
  77          *     [2] Route to Link 1
  78          *     [3] Route to Link 2
  79          * [11: 8] Response Route
  80          *     [0] Route to this node
  81          *     [1] Route to Link 0
  82          *     [2] Route to Link 1
  83          *     [3] Route to Link 2
  84          * [19:16] Broadcast route
  85          *     [0] Route to this node
  86          *     [1] Route to Link 0
  87          *     [2] Route to Link 1
  88          *     [3] Route to Link 2
  89          */
  90
  91         uint32_t ret = 0x00010101; /* default row entry */
  92
  93         static const unsigned int rows_2p[2][2] = {
  94                 { 0x00090101, 0x00010808 },
  95                 { 0x00010808, 0x00090101 }
  96         };
  97
  98         if (maxnodes > 2) {
  99                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 100                 maxnodes = 2;
 101         }
 102
 103
 104         if (!(node >= maxnodes || row >= maxnodes)) {
 105                 ret = rows_2p[node][row];
 106         }
 107
 108         return ret;
 109 }
 110
 111 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 112 {
 113         /* nothing to do */
 114 }
 115
 116 static inline int spd_read_byte(unsigned device, unsigned address)
 117 {
 118         return smbus_read_byte(device, address);
 119 }
 120
 121 #include "northbridge/amd/amdk8/raminit.c"
 122
 123 #include "northbridge/amd/amdk8/coherent_ht.c"
 124 #include "sdram/generic_sdram.c"
 125 #include "mainboard/ibm/e325/resourcemap.c"
 126
 127 #define FIRST_CPU  1
 128 #define SECOND_CPU 1
 129 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 130 static void main(void)
 131 {
 132         /*
 133          * GPIO28 of 8111 will control H0_MEMRESET_L
 134          * GPIO29 of 8111 will control H1_MEMRESET_L
 135          */
 136         static const struct mem_controller cpu[] = {
 137 #if FIRST_CPU
 138                 {
 139                         .node_id = 0,
 140                         .f0 = PCI_DEV(0, 0x18, 0),
 141                         .f1 = PCI_DEV(0, 0x18, 1),
 142                         .f2 = PCI_DEV(0, 0x18, 2),
 143                         .f3 = PCI_DEV(0, 0x18, 3),
 144                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 145                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 146                 },
 147 #endif
 148 #if SECOND_CPU
 149                 {
 150                         .node_id = 1,
 151                         .f0 = PCI_DEV(0, 0x19, 0),
 152                         .f1 = PCI_DEV(0, 0x19, 1),
 153                         .f2 = PCI_DEV(0, 0x19, 2),
 154                         .f3 = PCI_DEV(0, 0x19, 3),
 155                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 156                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 157                 },
 158 #endif
 159         };
 160         int needs_reset;
 161
 162         enable_lapic();
 163         init_timer();
 164         if (cpu_init_detected()) {
 165                 asm("jmp __cpu_reset");
 166         }
 167         distinguish_cpu_resets();
 168         if (!boot_cpu()) {
 169                 stop_this_cpu();
 170         }
 171         pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
 172         uart_init();
 173         console_init();
 174         setup_ibm_e325_resource_map();
 175         needs_reset = setup_coherent_ht_domain();
 176         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 177         if (needs_reset) {
 178                 print_info("ht reset -\r\n");
 179                 soft_reset();
 180         }
 181
 182 #if 0
 183         print_pci_devices();
 184 #endif
 185         enable_smbus();
 186 #if 0
 187         dump_spd_registers(&cpu[0]);
 188 #endif
 189         memreset_setup();
 190         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 191
 192 #if 0
 193         dump_pci_devices();
 194 #endif
 195 #if 0
 196         dump_pci_device(PCI_DEV(0, 0x18, 2));
 197 #endif
 198
 199
 200 #if 0
 201         /* Check the first 1M */
 202         ram_check(0x00000000, 0x001000000);
 203 #endif
 204
 205 }