1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_ROM_SECTION_SIZE
15 uses CONFIG_ROM_IMAGE_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
20 uses CONFIG_PRECOMPRESSED_PAYLOAD
22 uses CONFIG_XIP_ROM_SIZE
23 uses CONFIG_XIP_ROM_BASE
24 uses CONFIG_STACK_SIZE
26 uses CONFIG_USE_OPTION_TABLE
27 uses CONFIG_LB_CKS_RANGE_START
28 uses CONFIG_LB_CKS_RANGE_END
29 uses CONFIG_LB_CKS_LOC
30 uses CONFIG_MAINBOARD_PART_NUMBER
31 uses CONFIG_MAINBOARD_VENDOR
33 uses COREBOOT_EXTRA_VERSION
35 uses CONFIG_TTYS0_BAUD
36 uses CONFIG_TTYS0_BASE
38 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
39 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
40 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 uses CONFIG_CONSOLE_SERIAL8250
42 uses CONFIG_CROSS_COMPILE
46 uses CONFIG_USE_DCACHE_RAM
47 uses CONFIG_DCACHE_RAM_BASE
48 uses CONFIG_DCACHE_RAM_SIZE
50 uses CONFIG_USE_PRINTK_IN_CAR
58 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
60 default CONFIG_ROM_SIZE=524288
63 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
65 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
68 ## Build code for the fallback boot
70 default CONFIG_HAVE_FALLBACK_BOOT=1
73 ## Build code to reset the motherboard from coreboot
75 default CONFIG_HAVE_HARD_RESET=1
78 ## Build code to export a programmable irq routing table
80 default CONFIG_GENERATE_PIRQ_TABLE=1
81 default CONFIG_IRQ_SLOT_COUNT=12
84 ## Build code to export an x86 MP table
85 ## Useful for specifying IRQ routing values
87 default CONFIG_GENERATE_MP_TABLE=1
90 ## Build code to export a CMOS option table
92 default CONFIG_HAVE_OPTION_TABLE=1
95 ## Move the default coreboot cmos range off of AMD RTC registers
97 default CONFIG_LB_CKS_RANGE_START=49
98 default CONFIG_LB_CKS_RANGE_END=122
99 default CONFIG_LB_CKS_LOC=123
102 ## Build code for SMP support
103 ## Only worry about 2 micro processors
106 default CONFIG_MAX_CPUS=1
107 default CONFIG_MAX_PHYSICAL_CPUS=1
110 ## Build code to setup a generic IOAPIC
112 default CONFIG_IOAPIC=1
115 ## enable CACHE_AS_RAM specifics
117 default CONFIG_USE_DCACHE_RAM=1
118 default CONFIG_DCACHE_RAM_BASE=0xcf000
119 default CONFIG_DCACHE_RAM_SIZE=0x1000
120 default CONFIG_USE_INIT=0
123 ## Clean up the motherboard id strings
125 default CONFIG_MAINBOARD_PART_NUMBER="E325"
126 default CONFIG_MAINBOARD_VENDOR="IBM"
127 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
128 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
131 ### coreboot layout values
134 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
135 default CONFIG_ROM_IMAGE_SIZE = 65536
138 ## Use a small 8K stack
140 default CONFIG_STACK_SIZE=0x2000
143 ## Use a small 16K heap
145 default CONFIG_HEAP_SIZE=0x8000
148 ## Only use the option table in a normal image
150 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
153 ## Coreboot C code runs at this location in RAM
155 default CONFIG_RAMBASE=0x00004000
158 ## Load the payload from the ROM
160 default CONFIG_ROM_PAYLOAD = 1
163 ### Defaults of options that you may want to override in the target config file
167 ## The default compiler
169 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
172 default CONFIG_USE_PRINTK_IN_CAR=1
175 ## The Serial Console
178 # To Enable the Serial Console
179 default CONFIG_CONSOLE_SERIAL8250=1
181 ## Select the serial console baud rate
182 default CONFIG_TTYS0_BAUD=115200
183 #default CONFIG_TTYS0_BAUD=57600
184 #default CONFIG_TTYS0_BAUD=38400
185 #default CONFIG_TTYS0_BAUD=19200
186 #default CONFIG_TTYS0_BAUD=9600
187 #default CONFIG_TTYS0_BAUD=4800
188 #default CONFIG_TTYS0_BAUD=2400
189 #default CONFIG_TTYS0_BAUD=1200
191 # Select the serial console base port
192 default CONFIG_TTYS0_BASE=0x3f8
194 # Select the serial protocol
195 # This defaults to 8 data bits, 1 stop bit, and no parity
196 default CONFIG_TTYS0_LCS=0x3
199 ### Select the coreboot loglevel
201 ## EMERG 1 system is unusable
202 ## ALERT 2 action must be taken immediately
203 ## CRIT 3 critical conditions
204 ## ERR 4 error conditions
205 ## WARNING 5 warning conditions
206 ## NOTICE 6 normal but significant condition
207 ## INFO 7 informational
208 ## CONFIG_DEBUG 8 debug-level messages
209 ## SPEW 9 Way too many details
211 ## Request this level of debugging output
212 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
213 ## At a maximum only compile in this level of debugging
214 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
217 ## Select power on after power fail setting
218 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"