1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_ROM_SECTION_SIZE
15 uses CONFIG_ROM_IMAGE_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
22 uses CONFIG_PAYLOAD_SIZE
24 uses CONFIG_XIP_ROM_SIZE
25 uses CONFIG_XIP_ROM_BASE
26 uses CONFIG_STACK_SIZE
28 uses CONFIG_USE_OPTION_TABLE
29 uses CONFIG_LB_CKS_RANGE_START
30 uses CONFIG_LB_CKS_RANGE_END
31 uses CONFIG_LB_CKS_LOC
32 uses CONFIG_MAINBOARD_PART_NUMBER
33 uses CONFIG_MAINBOARD_VENDOR
35 uses COREBOOT_EXTRA_VERSION
37 uses CONFIG_TTYS0_BAUD
38 uses CONFIG_TTYS0_BASE
40 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
41 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
42 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
43 uses CONFIG_CONSOLE_SERIAL8250
44 uses CONFIG_CROSS_COMPILE
48 uses CONFIG_USE_DCACHE_RAM
49 uses CONFIG_DCACHE_RAM_BASE
50 uses CONFIG_DCACHE_RAM_SIZE
52 uses CONFIG_USE_PRINTK_IN_CAR
60 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
62 default CONFIG_ROM_SIZE=524288
65 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
67 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
70 ## Build code for the fallback boot
72 default CONFIG_HAVE_FALLBACK_BOOT=1
75 ## Build code to reset the motherboard from coreboot
77 default CONFIG_HAVE_HARD_RESET=1
80 ## Build code to export a programmable irq routing table
82 default CONFIG_HAVE_PIRQ_TABLE=1
83 default CONFIG_IRQ_SLOT_COUNT=9
86 ## Build code to export an x86 MP table
87 ## Useful for specifying IRQ routing values
89 default CONFIG_HAVE_MP_TABLE=1
92 ## Build code to export a CMOS option table
94 default CONFIG_HAVE_OPTION_TABLE=1
97 ## Move the default coreboot cmos range off of AMD RTC registers
99 default CONFIG_LB_CKS_RANGE_START=49
100 default CONFIG_LB_CKS_RANGE_END=122
101 default CONFIG_LB_CKS_LOC=123
104 ## Build code for SMP support
105 ## Only worry about 2 micro processors
108 default CONFIG_MAX_CPUS=1
109 default CONFIG_MAX_PHYSICAL_CPUS=1
112 ## Build code to setup a generic IOAPIC
114 default CONFIG_IOAPIC=1
117 ## enable CACHE_AS_RAM specifics
119 default CONFIG_USE_DCACHE_RAM=1
120 default CONFIG_DCACHE_RAM_BASE=0xcf000
121 default CONFIG_DCACHE_RAM_SIZE=0x1000
122 default CONFIG_USE_INIT=0
125 ## Clean up the motherboard id strings
127 default CONFIG_MAINBOARD_PART_NUMBER="E325"
128 default CONFIG_MAINBOARD_VENDOR="IBM"
129 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
130 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
133 ### coreboot layout values
136 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
137 default CONFIG_ROM_IMAGE_SIZE = 65536
140 ## Use a small 8K stack
142 default CONFIG_STACK_SIZE=0x2000
145 ## Use a small 16K heap
147 default CONFIG_HEAP_SIZE=0x8000
150 ## Only use the option table in a normal image
152 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
155 ## Coreboot C code runs at this location in RAM
157 default CONFIG_RAMBASE=0x00004000
160 ## Load the payload from the ROM
162 default CONFIG_ROM_PAYLOAD = 1
165 ### Defaults of options that you may want to override in the target config file
169 ## The default compiler
171 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
174 default CONFIG_USE_PRINTK_IN_CAR=1
177 ## The Serial Console
180 # To Enable the Serial Console
181 default CONFIG_CONSOLE_SERIAL8250=1
183 ## Select the serial console baud rate
184 default CONFIG_TTYS0_BAUD=115200
185 #default CONFIG_TTYS0_BAUD=57600
186 #default CONFIG_TTYS0_BAUD=38400
187 #default CONFIG_TTYS0_BAUD=19200
188 #default CONFIG_TTYS0_BAUD=9600
189 #default CONFIG_TTYS0_BAUD=4800
190 #default CONFIG_TTYS0_BAUD=2400
191 #default CONFIG_TTYS0_BAUD=1200
193 # Select the serial console base port
194 default CONFIG_TTYS0_BASE=0x3f8
196 # Select the serial protocol
197 # This defaults to 8 data bits, 1 stop bit, and no parity
198 default CONFIG_TTYS0_LCS=0x3
201 ### Select the coreboot loglevel
203 ## EMERG 1 system is unusable
204 ## ALERT 2 action must be taken immediately
205 ## CRIT 3 critical conditions
206 ## ERR 4 error conditions
207 ## WARNING 5 warning conditions
208 ## NOTICE 6 normal but significant condition
209 ## INFO 7 informational
210 ## CONFIG_DEBUG 8 debug-level messages
211 ## SPEW 9 Way too many details
213 ## Request this level of debugging output
214 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
215 ## At a maximum only compile in this level of debugging
216 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
219 ## Select power on after power fail setting
220 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"