2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2010 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
22 /* Configuration of the i945 driver */
23 #define CHIPSET_I945GM 1
24 //#define OVERRIDE_CLOCK_DISABLE 1
25 #define CHANNEL_XOR_RANDOMIZATION 1
30 #include <arch/romcc_io.h>
31 #include <device/pci_def.h>
32 #include <device/pnp_def.h>
33 #include <cpu/x86/lapic.h>
35 #include "superio/winbond/w83627ehg/w83627ehg.h"
37 #include "option_table.h"
38 #include "pc80/mc146818rtc_early.c"
40 #include <console/console.h>
41 #include <cpu/x86/bist.h>
44 #define DBGP_DEFAULT 1
45 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
46 #include "pc80/usbdebug_serial.c"
49 #include "lib/ramtest.c"
50 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
51 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
53 #include "northbridge/intel/i945/udelay.c"
55 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
57 #include "southbridge/intel/i82801gx/i82801gx.h"
58 static void setup_ich7_gpios(void)
60 printk(BIOS_DEBUG, " GPIOS...");
61 /* General Registers */
62 outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
63 outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
64 outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
65 /* Output Control Registers */
66 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
67 /* Input Control Registers */
68 outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
69 outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
70 outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
71 outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
74 #include "northbridge/intel/i945/early_init.c"
76 static inline int spd_read_byte(unsigned device, unsigned address)
78 return smbus_read_byte(device, address);
81 #include "northbridge/intel/i945/raminit.h"
82 #include "northbridge/intel/i945/raminit.c"
83 #include "northbridge/intel/i945/errata.c"
84 #include "northbridge/intel/i945/debug.c"
86 static void ich7_enable_lpc(void)
89 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
90 // Set COM1/COM2 decode range
91 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
92 // Enable COM1/COM2/KBD/SuperIO1+2
93 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
94 // Enable HWM at 0x290
95 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
97 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
100 /* This box has one superio
101 * Also set up the GPIOs from the beginning. This is the "no schematic
102 * but safe anyways" method.
104 static void early_superio_config_w83627ehg(void)
108 dev=PNP_DEV(0x4e, W83627EHG_SP1);
109 pnp_enter_ext_func_mode(dev);
111 pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
113 pnp_write_config(dev, 0x29, 0x01); // GPIO settings
114 pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
115 pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
116 pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
117 pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
119 dev=PNP_DEV(0x4e, W83627EHG_SP1);
120 pnp_set_logical_device(dev);
121 pnp_set_enable(dev, 0);
122 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
123 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
124 pnp_set_enable(dev, 1);
126 dev=PNP_DEV(0x4e, W83627EHG_SP2);
127 pnp_set_logical_device(dev);
128 pnp_set_enable(dev, 0);
129 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
130 pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
131 // pnp_write_config(dev, 0xf1, 4); // IRMODE0
132 pnp_set_enable(dev, 1);
134 dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
135 pnp_set_logical_device(dev);
136 pnp_set_enable(dev, 0);
137 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
138 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
139 //pnp_write_config(dev, 0xf0, 0x82);
140 pnp_set_enable(dev, 1);
142 dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
143 pnp_set_logical_device(dev);
144 pnp_set_enable(dev, 1); // Just enable it
146 dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
147 pnp_set_logical_device(dev);
148 pnp_set_enable(dev, 0);
149 pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
150 pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
151 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
153 dev=PNP_DEV(0x4e, W83627EHG_FDC);
154 pnp_set_logical_device(dev);
155 pnp_set_enable(dev, 0);
157 dev=PNP_DEV(0x4e, W83627EHG_PP);
158 pnp_set_logical_device(dev);
159 pnp_set_enable(dev, 0);
162 dev=PNP_DEV(0x4e, W83627EHG_HWM);
163 pnp_set_logical_device(dev);
164 pnp_set_enable(dev, 0);
165 pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
166 pnp_set_enable(dev, 1);
168 pnp_exit_ext_func_mode(dev);
171 static void rcba_config(void)
173 /* Set up virtual channel 0 */
174 //RCBA32(0x0014) = 0x80000001;
175 //RCBA32(0x001c) = 0x03128010;
177 /* Device 1f interrupt pin register */
178 RCBA32(0x3100) = 0x00042210;
179 /* Device 1d interrupt pin register */
180 RCBA32(0x310c) = 0x00214321;
182 /* dev irq route register */
183 RCBA16(0x3140) = 0x0132;
184 RCBA16(0x3142) = 0x0146;
185 RCBA16(0x3144) = 0x0237;
186 RCBA16(0x3146) = 0x3201;
187 RCBA16(0x3148) = 0x0146;
190 RCBA8(0x31ff) = 0x03;
192 /* Enable upper 128bytes of CMOS */
193 RCBA32(0x3400) = (1 << 2);
195 /* Enable PCIe Root Port Clock Gate */
196 // RCBA32(0x341c) = 0x00000001;
199 static void early_ich7_init(void)
204 // program secondary mlt XXX byte?
205 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
207 // reset rtc power status
208 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
210 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
212 // usb transient disconnect
213 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
215 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
217 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
218 reg32 |= (1 << 29) | (1 << 17);
219 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
221 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
222 reg32 |= (1 << 31) | (1 << 27);
223 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
225 RCBA32(0x0088) = 0x0011d000;
226 RCBA16(0x01fc) = 0x060f;
227 RCBA32(0x01f4) = 0x86000040;
228 RCBA32(0x0214) = 0x10030549;
229 RCBA32(0x0218) = 0x00020504;
230 RCBA8(0x0220) = 0xc5;
231 reg32 = RCBA32(0x3410);
233 RCBA32(0x3410) = reg32;
234 reg32 = RCBA32(0x3430);
237 RCBA32(0x3430) = reg32;
238 RCBA32(0x3418) |= (1 << 0);
239 RCBA16(0x0200) = 0x2008;
240 RCBA8(0x2027) = 0x0d;
241 RCBA16(0x3e08) |= (1 << 7);
242 RCBA16(0x3e48) |= (1 << 7);
243 RCBA32(0x3e0e) |= (1 << 7);
244 RCBA32(0x3e4e) |= (1 << 7);
246 // next step only on ich7m b0 and later:
247 reg32 = RCBA32(0x2034);
248 reg32 &= ~(0x0f << 16);
250 RCBA32(0x2034) = reg32;
255 // Now, this needs to be included because it relies on the symbol
256 // __PRE_RAM__ being set during CAR stage (in order to compile the
257 // BSS free versions of the functions). Either rewrite the code
258 // to be always BSS free, or invent a flag that's better suited than
259 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
261 #include "lib/cbmem.c"
263 void main(unsigned long bist)
273 early_superio_config_w83627ehg();
275 /* Set up the console */
279 i82801gx_enable_usbdebug(DBGP_DEFAULT);
280 early_usbdebug_init();
285 /* Halt if there was a built in self test failure */
286 report_bist_failure(bist);
288 if (MCHBAR16(SSKPD) == 0xCAFE) {
289 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
291 while (1) asm("hlt");
294 /* Perform some early chipset initialization required
295 * before RAM initialization can work
297 i945_early_initialization();
300 reg32 = inl(DEFAULT_PMBASE + 0x04);
301 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
302 if (((reg32 >> 10) & 7) == 5) {
303 #if CONFIG_HAVE_ACPI_RESUME
304 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
306 /* Clear SLP_TYPE. This will break stage2 but
307 * we care for that when we get there.
309 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
311 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
315 /* Enable SPD ROMs and DDR-II DRAM */
318 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
319 dump_spd_registers();
322 sdram_initialize(boot_mode);
324 /* Perform some initialization that must run before stage2 */
327 /* This should probably go away. Until now it is required
328 * and mainboard specific
332 /* Chipset Errata! */
335 /* Initialize the internal PCIe links before we go into stage2 */
336 i945_late_initialization();
338 #if !CONFIG_HAVE_ACPI_RESUME
339 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
340 #if CONFIG_DEBUG_RAM_SETUP
341 sdram_dump_mchbar_registers();
345 /* This will not work if TSEG is in place! */
346 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
348 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
349 ram_check(0x00000000, 0x000a0000);
350 //ram_check(0x00100000, tom);
357 MCHBAR16(SSKPD) = 0xCAFE;
359 #if CONFIG_HAVE_ACPI_RESUME
360 /* Start address of high memory tables */
361 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
363 /* If there is no high memory area, we didn't boot before, so
364 * this is not a resume. In that case we just create the cbmem toc.
366 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
367 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
369 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
370 * through stage 2. We could keep stuff like stack and heap in high tables
371 * memory completely, but that's a wonderful clean up task for another
374 if (resume_backup_memory)
375 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
377 /* Magic for S3 resume */
378 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);