src/mainboard/ibase/mb899/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  21
  22 /* Configuration of the i945 driver */
  23 #define CHIPSET_I945GM 1
  24 //#define OVERRIDE_CLOCK_DISABLE 1
  25 #define CHANNEL_XOR_RANDOMIZATION 1
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <arch/io.h>
  30 #include <arch/romcc_io.h>
  31 #include <device/pci_def.h>
  32 #include <device/pnp_def.h>
  33 #include <cpu/x86/lapic.h>
  34
  35 #include "superio/winbond/w83627ehg/w83627ehg.h"
  36
  37 #include <pc80/mc146818rtc.h>
  38
  39 #include <console/console.h>
  40 #include <cpu/x86/bist.h>
  41
  42 #if CONFIG_USBDEBUG
  43 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
  44 #include "pc80/usbdebug_serial.c"
  45 #endif
  46
  47 #include "lib/ramtest.c"
  48 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
  49 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  50
  51 #include "northbridge/intel/i945/udelay.c"
  52
  53 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
  54
  55 #include "southbridge/intel/i82801gx/i82801gx.h"
  56 static void setup_ich7_gpios(void)
  57 {
  58         printk(BIOS_DEBUG, " GPIOS...");
  59         /* General Registers */
  60         outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  61         outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  62         outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  63         /* Output Control Registers */
  64         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  65         /* Input Control Registers */
  66         outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  67         outl(0x000100ff, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  68         outl(0x00000030, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  69         outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
  70 }
  71
  72 #include "northbridge/intel/i945/early_init.c"
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/intel/i945/raminit.h"
  80 #include "northbridge/intel/i945/raminit.c"
  81 #include "northbridge/intel/i945/errata.c"
  82 #include "northbridge/intel/i945/debug.c"
  83
  84 static void ich7_enable_lpc(void)
  85 {
  86         // Enable Serial IRQ
  87         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
  88         // Set COM1/COM2 decode range
  89         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
  90         // Enable COM1/COM2/KBD/SuperIO1+2
  91         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
  92         // Enable HWM at 0x290
  93         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
  94         // io 0x300 decode
  95         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
  96 }
  97
  98 /* This box has one superio
  99  * Also set up the GPIOs from the beginning. This is the "no schematic
 100  * but safe anyways" method.
 101  */
 102 static void early_superio_config_w83627ehg(void)
 103 {
 104         device_t dev;
 105
 106         dev=PNP_DEV(0x4e, W83627EHG_SP1);
 107         pnp_enter_ext_func_mode(dev);
 108
 109         pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
 110
 111         pnp_write_config(dev, 0x29, 0x01); // GPIO settings
 112         pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
 113         pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
 114         pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
 115         pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
 116
 117         dev=PNP_DEV(0x4e, W83627EHG_SP1);
 118         pnp_set_logical_device(dev);
 119         pnp_set_enable(dev, 0);
 120         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
 121         pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
 122         pnp_set_enable(dev, 1);
 123
 124         dev=PNP_DEV(0x4e, W83627EHG_SP2);
 125         pnp_set_logical_device(dev);
 126         pnp_set_enable(dev, 0);
 127         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
 128         pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
 129         // pnp_write_config(dev, 0xf1, 4); // IRMODE0
 130         pnp_set_enable(dev, 1);
 131
 132         dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
 133         pnp_set_logical_device(dev);
 134         pnp_set_enable(dev, 0);
 135         pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
 136         pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
 137         //pnp_write_config(dev, 0xf0, 0x82);
 138         pnp_set_enable(dev, 1);
 139
 140         dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
 141         pnp_set_logical_device(dev);
 142         pnp_set_enable(dev, 1); // Just enable it
 143
 144         dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
 145         pnp_set_logical_device(dev);
 146         pnp_set_enable(dev, 0);
 147         pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
 148         pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
 149         pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
 150
 151         dev=PNP_DEV(0x4e, W83627EHG_FDC);
 152         pnp_set_logical_device(dev);
 153         pnp_set_enable(dev, 0);
 154
 155         dev=PNP_DEV(0x4e, W83627EHG_PP);
 156         pnp_set_logical_device(dev);
 157         pnp_set_enable(dev, 0);
 158
 159         /* Enable HWM */
 160         dev=PNP_DEV(0x4e, W83627EHG_HWM);
 161         pnp_set_logical_device(dev);
 162         pnp_set_enable(dev, 0);
 163         pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
 164         pnp_set_enable(dev, 1);
 165
 166         pnp_exit_ext_func_mode(dev);
 167 }
 168
 169 static void rcba_config(void)
 170 {
 171         /* Set up virtual channel 0 */
 172         //RCBA32(0x0014) = 0x80000001;
 173         //RCBA32(0x001c) = 0x03128010;
 174
 175         /* Device 1f interrupt pin register */
 176         RCBA32(0x3100) = 0x00042210;
 177         /* Device 1d interrupt pin register */
 178         RCBA32(0x310c) = 0x00214321;
 179
 180         /* dev irq route register */
 181         RCBA16(0x3140) = 0x0132;
 182         RCBA16(0x3142) = 0x0146;
 183         RCBA16(0x3144) = 0x0237;
 184         RCBA16(0x3146) = 0x3201;
 185         RCBA16(0x3148) = 0x0146;
 186
 187         /* Enable IOAPIC */
 188         RCBA8(0x31ff) = 0x03;
 189
 190         /* Enable upper 128bytes of CMOS */
 191         RCBA32(0x3400) = (1 << 2);
 192
 193         /* Enable PCIe Root Port Clock Gate */
 194         // RCBA32(0x341c) = 0x00000001;
 195 }
 196
 197 static void early_ich7_init(void)
 198 {
 199         uint8_t reg8;
 200         uint32_t reg32;
 201
 202         // program secondary mlt XXX byte?
 203         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 204
 205         // reset rtc power status
 206         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 207         reg8 &= ~(1 << 2);
 208         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 209
 210         // usb transient disconnect
 211         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 212         reg8 |= (3 << 0);
 213         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 214
 215         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 216         reg32 |= (1 << 29) | (1 << 17);
 217         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 218
 219         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 220         reg32 |= (1 << 31) | (1 << 27);
 221         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 222
 223         RCBA32(0x0088) = 0x0011d000;
 224         RCBA16(0x01fc) = 0x060f;
 225         RCBA32(0x01f4) = 0x86000040;
 226         RCBA32(0x0214) = 0x10030549;
 227         RCBA32(0x0218) = 0x00020504;
 228         RCBA8(0x0220) = 0xc5;
 229         reg32 = RCBA32(0x3410);
 230         reg32 |= (1 << 6);
 231         RCBA32(0x3410) = reg32;
 232         reg32 = RCBA32(0x3430);
 233         reg32 &= ~(3 << 0);
 234         reg32 |= (1 << 0);
 235         RCBA32(0x3430) = reg32;
 236         RCBA32(0x3418) |= (1 << 0);
 237         RCBA16(0x0200) = 0x2008;
 238         RCBA8(0x2027) = 0x0d;
 239         RCBA16(0x3e08) |= (1 << 7);
 240         RCBA16(0x3e48) |= (1 << 7);
 241         RCBA32(0x3e0e) |= (1 << 7);
 242         RCBA32(0x3e4e) |= (1 << 7);
 243
 244         // next step only on ich7m b0 and later:
 245         reg32 = RCBA32(0x2034);
 246         reg32 &= ~(0x0f << 16);
 247         reg32 |= (5 << 16);
 248         RCBA32(0x2034) = reg32;
 249 }
 250
 251 #include <cbmem.h>
 252
 253 // Now, this needs to be included because it relies on the symbol
 254 // __PRE_RAM__ being set during CAR stage (in order to compile the
 255 // BSS free versions of the functions). Either rewrite the code
 256 // to be always BSS free, or invent a flag that's better suited than
 257 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
 258 //
 259 #include "lib/cbmem.c"
 260
 261 void main(unsigned long bist)
 262 {
 263         u32 reg32;
 264         int boot_mode = 0;
 265
 266         if (bist == 0) {
 267                 enable_lapic();
 268         }
 269
 270         ich7_enable_lpc();
 271         early_superio_config_w83627ehg();
 272
 273         /* Set up the console */
 274         uart_init();
 275
 276 #if CONFIG_USBDEBUG
 277         i82801gx_enable_usbdebug(1);
 278         early_usbdebug_init();
 279 #endif
 280
 281         console_init();
 282
 283         /* Halt if there was a built in self test failure */
 284         report_bist_failure(bist);
 285
 286         if (MCHBAR16(SSKPD) == 0xCAFE) {
 287                 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 288                 outb(0x6, 0xcf9);
 289                 while (1) asm("hlt");
 290         }
 291
 292         /* Perform some early chipset initialization required
 293          * before RAM initialization can work
 294          */
 295         i945_early_initialization();
 296
 297         /* Read PM1_CNT */
 298         reg32 = inl(DEFAULT_PMBASE + 0x04);
 299         printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 300         if (((reg32 >> 10) & 7) == 5) {
 301 #if CONFIG_HAVE_ACPI_RESUME
 302                 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 303                 boot_mode = 2;
 304                 /* Clear SLP_TYPE. This will break stage2 but
 305                  * we care for that when we get there.
 306                  */
 307                 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 308 #else
 309                 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 310 #endif
 311         }
 312
 313         /* Enable SPD ROMs and DDR-II DRAM */
 314         enable_smbus();
 315
 316 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 317         dump_spd_registers();
 318 #endif
 319
 320         sdram_initialize(boot_mode);
 321
 322         /* Perform some initialization that must run before stage2 */
 323         early_ich7_init();
 324
 325         /* This should probably go away. Until now it is required
 326          * and mainboard specific
 327          */
 328         rcba_config();
 329
 330         /* Chipset Errata! */
 331         fixup_i945_errata();
 332
 333         /* Initialize the internal PCIe links before we go into stage2 */
 334         i945_late_initialization();
 335
 336 #if !CONFIG_HAVE_ACPI_RESUME
 337 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 338 #if CONFIG_DEBUG_RAM_SETUP
 339         sdram_dump_mchbar_registers();
 340 #endif
 341
 342         {
 343                 /* This will not work if TSEG is in place! */
 344                 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 345
 346                 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 347                 ram_check(0x00000000, 0x000a0000);
 348                 //ram_check(0x00100000, tom);
 349         }
 350 #endif
 351 #endif
 352
 353         quick_ram_check();
 354
 355         MCHBAR16(SSKPD) = 0xCAFE;
 356
 357 #if CONFIG_HAVE_ACPI_RESUME
 358         /* Start address of high memory tables */
 359         unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
 360
 361         /* If there is no high memory area, we didn't boot before, so
 362          * this is not a resume. In that case we just create the cbmem toc.
 363          */
 364         if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
 365                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 366
 367                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 368                  * through stage 2. We could keep stuff like stack and heap in high tables
 369                  * memory completely, but that's a wonderful clean up task for another
 370                  * day.
 371                  */
 372                 if (resume_backup_memory)
 373                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 374
 375                 /* Magic for S3 resume */
 376                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
 377         }
 378 #endif
 379 }
 380