src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #define ASSEMBLY 1
  29
  30
  31 #define RAMINIT_SYSINFO 1
  32
  33 #define K8_ALLOCATE_IO_RANGE 1
  34
  35 #define QRANK_DIMM_SUPPORT 1
  36
  37 #if CONFIG_LOGICAL_CPUS==1
  38 #define SET_NB_CFG_54 1
  39 #endif
  40
  41 //used by init_cpus and fidvid
  42 #define K8_SET_FIDVID 1
  43 //if we want to wait for core1 done before DQS training, set it to 0
  44 #define K8_SET_FIDVID_CORE0_ONLY 1
  45
  46 #if CONFIG_K8_REV_F_SUPPORT == 1
  47 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  48 #endif
  49
  50 #define DBGP_DEFAULT 7
  51
  52 #include <stdint.h>
  53 #include <string.h>
  54 #include <device/pci_def.h>
  55 #include <device/pci_ids.h>
  56 #include <arch/io.h>
  57 #include <device/pnp_def.h>
  58 #include <arch/romcc_io.h>
  59 #include <cpu/x86/lapic.h>
  60 #include "option_table.h"
  61 #include "pc80/mc146818rtc_early.c"
  62
  63
  64 #include "pc80/serial.c"
  65 #include "arch/i386/lib/console.c"
  66 #include "lib/ramtest.c"
  67
  68 #include <cpu/amd/model_fxx_rev.h>
  69
  70 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  71 #include "northbridge/amd/amdk8/raminit.h"
  72 #include "cpu/amd/model_fxx/apic_timer.c"
  73 #include "lib/delay.c"
  74
  75 #include "cpu/x86/lapic/boot_cpu.c"
  76 #include "northbridge/amd/amdk8/reset_test.c"
  77
  78 #include "superio/serverengines/pilot/pilot_early_serial.c"
  79 #include "superio/serverengines/pilot/pilot_early_init.c"
  80 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  81
  82
  83 #include "cpu/x86/bist.h"
  84
  85 #include "northbridge/amd/amdk8/debug.c"
  86
  87 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  88
  89 #include "northbridge/amd/amdk8/setup_resource_map.c"
  90
  91 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  92 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  93
  94 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  95
  96 static void memreset_setup(void)
  97 {
  98 }
  99
 100 static void memreset(int controllers, const struct mem_controller *ctrl)
 101 {
 102 }
 103
 104 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 105 {
 106 #define SMBUS_SWITCH1 0x70
 107 #define SMBUS_SWITCH2 0x72
 108          unsigned device = (ctrl->channel0[0]) >> 8;
 109          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
 110          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
 111 }
 112
 113 static inline int spd_read_byte(unsigned device, unsigned address)
 114 {
 115          return smbus_read_byte(device, address);
 116 }
 117
 118 #include "northbridge/amd/amdk8/amdk8_f.h"
 119 #include "northbridge/amd/amdk8/coherent_ht.c"
 120
 121 #include "northbridge/amd/amdk8/incoherent_ht.c"
 122
 123 #include "northbridge/amd/amdk8/raminit_f.c"
 124
 125 #include "lib/generic_sdram.c"
 126
 127 //#include "resourcemap.c"
 128
 129 #include "cpu/amd/dualcore/dualcore.c"
 130
 131 //first node
 132 #define DIMM0 0x50
 133 #define DIMM1 0x51
 134 #define DIMM2 0x52
 135 #define DIMM3 0x53
 136 //second node
 137 #define DIMM4 0x54
 138 #define DIMM5 0x55
 139 #define DIMM6 0x56
 140 #define DIMM7 0x57
 141
 142
 143 #include "cpu/amd/car/copy_and_run.c"
 144
 145 #include "cpu/amd/car/post_cache_as_ram.c"
 146
 147 #include "cpu/amd/model_fxx/init_cpus.c"
 148
 149 #include "cpu/amd/model_fxx/fidvid.c"
 150
 151 #include "northbridge/amd/amdk8/early_ht.c"
 152
 153 #if 0
 154 #include "ipmi.c"
 155
 156 static void setup_early_ipmi_serial()
 157 {
 158         unsigned char result;
 159         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 160         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 161         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 162         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 163         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 164
 165 //      earlydbg(0x0d);
 166         //set channel access system only
 167         ipmi_request(5,channel_access);
 168 //      earlydbg(result);
 169 /*
 170         //Set serial/modem config
 171         result=ipmi_request(6,serialmodem_conf);
 172         earlydbg(result);
 173
 174         //Set serial mux 1
 175         result=ipmi_request(4,serial_mux1);
 176         earlydbg(result);
 177
 178         //Set serial mux 2
 179         result=ipmi_request(4,serial_mux2);
 180         earlydbg(result);
 181
 182         //Set serial mux 3
 183         result=ipmi_request(4,serial_mux3);
 184         earlydbg(result);
 185 */
 186 //      earlydbg(0x0e);
 187
 188 }
 189 #endif
 190
 191 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 192 {
 193         static const uint16_t spd_addr[] = {
 194                 //first node
 195                  DIMM0, DIMM2, 0, 0,
 196                  DIMM1, DIMM3, 0, 0,
 197 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 198                 //second node
 199                 DIMM4, DIMM6, 0, 0,
 200                 DIMM5, DIMM7, 0, 0,
 201 #endif
 202
 203         };
 204
 205         struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 206
 207          int needs_reset;
 208          unsigned bsp_apicid = 0;
 209
 210          if (!cpu_init_detectedx && boot_cpu()) {
 211                  /* Nothing special needs to be done to find bus 0 */
 212                  /* Allow the HT devices to be found */
 213
 214                  enumerate_ht_chain();
 215                  bcm5785_enable_rom();
 216                  bcm5785_enable_lpc();
 217                  //enable RTC
 218                 pc87417_enable_dev(RTC_DEV);
 219          }
 220
 221
 222          if (bist == 0) {
 223                  bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 224          }
 225
 226         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 227
 228         //setup_mp_resource_map();
 229
 230         uart_init();
 231
 232         /* Halt if there was a built in self test failure */
 233         report_bist_failure(bist);
 234
 235
 236         console_init();
 237 //      setup_early_ipmi_serial();
 238         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 239         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 240
 241         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 242
 243 #if CONFIG_MEM_TRAIN_SEQ == 1
 244         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 245 #endif
 246         setup_coherent_ht_domain();
 247
 248         wait_all_core0_started();
 249 #if CONFIG_LOGICAL_CPUS==1
 250         // It is said that we should start core1 after all core0 launched
 251         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 252          * So here need to make sure last core0 is started, esp for two way system,
 253          * (there may be apic id conflicts in that case)
 254         */
 255         start_other_cores();
 256         wait_all_other_cores_started(bsp_apicid);
 257 #endif
 258
 259         /* it will set up chains and store link pair for optimization later */
 260         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 261         bcm5785_early_setup();
 262
 263 #if K8_SET_FIDVID == 1
 264         {
 265                 msr_t msr;
 266                 msr=rdmsr(0xc0010042);
 267                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 268         }
 269         enable_fid_change();
 270         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 271         init_fidvid_bsp(bsp_apicid);
 272         // show final fid and vid
 273         {
 274                 msr_t msr;
 275                 msr=rdmsr(0xc0010042);
 276                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 277         }
 278 #endif
 279
 280         needs_reset = optimize_link_coherent_ht();
 281         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 282
 283         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 284         if (needs_reset) {
 285                 print_info("ht reset -\r\n");
 286                 soft_reset();
 287         }
 288
 289         allow_all_aps_stop(bsp_apicid);
 290
 291         //It's the time to set ctrl in sysinfo now;
 292         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 293         enable_smbus();
 294
 295         memreset_setup();
 296         //do we need apci timer, tsc...., only debug need it for better output
 297         /* all ap stopped? */
 298 //      init_timer(); // Need to use TMICT to synconize FID/VID
 299
 300         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 301
 302         post_cache_as_ram();
 303
 304 }
 305