src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #define K8_ALLOCATE_IO_RANGE 1
  29
  30
  31 #if CONFIG_LOGICAL_CPUS==1
  32 #define SET_NB_CFG_54 1
  33 #endif
  34
  35 //used by init_cpus and fidvid
  36 #define SET_FIDVID 1
  37 //if we want to wait for core1 done before DQS training, set it to 0
  38 #define SET_FIDVID_CORE0_ONLY 1
  39
  40 #if CONFIG_K8_REV_F_SUPPORT == 1
  41 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  42 #endif
  43
  44 #include <stdint.h>
  45 #include <string.h>
  46 #include <device/pci_def.h>
  47 #include <device/pci_ids.h>
  48 #include <arch/io.h>
  49 #include <device/pnp_def.h>
  50 #include <arch/romcc_io.h>
  51 #include <cpu/x86/lapic.h>
  52 #include <pc80/mc146818rtc.h>
  53
  54 #include <console/console.h>
  55
  56 #include <cpu/amd/model_fxx_rev.h>
  57
  58 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  59 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  60 #include "northbridge/amd/amdk8/raminit.h"
  61 #include "cpu/amd/model_fxx/apic_timer.c"
  62 #include "lib/delay.c"
  63
  64 #include "cpu/x86/lapic/boot_cpu.c"
  65 #include "northbridge/amd/amdk8/reset_test.c"
  66
  67 #include "superio/serverengines/pilot/pilot_early_serial.c"
  68 #include "superio/serverengines/pilot/pilot_early_init.c"
  69 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  70
  71 #include "cpu/x86/bist.h"
  72
  73 #include "northbridge/amd/amdk8/debug.c"
  74
  75 #include "cpu/x86/mtrr/earlymtrr.c"
  76
  77 #include "northbridge/amd/amdk8/setup_resource_map.c"
  78
  79 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  80 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  81
  82 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  83
  84 static void memreset(int controllers, const struct mem_controller *ctrl)
  85 {
  86 }
  87
  88 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  89 {
  90 #define SMBUS_SWITCH1 0x70
  91 #define SMBUS_SWITCH2 0x72
  92          unsigned device = (ctrl->channel0[0]) >> 8;
  93          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  94          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  95 }
  96
  97 static inline int spd_read_byte(unsigned device, unsigned address)
  98 {
  99          return smbus_read_byte(device, address);
 100 }
 101
 102 #include "northbridge/amd/amdk8/amdk8_f.h"
 103 #include "northbridge/amd/amdk8/incoherent_ht.c"
 104 #include "northbridge/amd/amdk8/coherent_ht.c"
 105 #include "northbridge/amd/amdk8/raminit_f.c"
 106 #include "lib/generic_sdram.c"
 107
 108 #include "cpu/amd/dualcore/dualcore.c"
 109
 110 //first node
 111 #define DIMM0 0x50
 112 #define DIMM1 0x51
 113 #define DIMM2 0x52
 114 #define DIMM3 0x53
 115 //second node
 116 #define DIMM4 0x54
 117 #define DIMM5 0x55
 118 #define DIMM6 0x56
 119 #define DIMM7 0x57
 120
 121
 122
 123 #include "cpu/amd/car/post_cache_as_ram.c"
 124
 125 #include "cpu/amd/model_fxx/init_cpus.c"
 126
 127 #include "cpu/amd/model_fxx/fidvid.c"
 128
 129 #include "northbridge/amd/amdk8/early_ht.c"
 130
 131 #if 0
 132 #include "ipmi.c"
 133
 134 static void setup_early_ipmi_serial()
 135 {
 136         unsigned char result;
 137         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 138         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 139         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 140         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 141         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 142
 143 //      earlydbg(0x0d);
 144         //set channel access system only
 145         ipmi_request(5,channel_access);
 146 //      earlydbg(result);
 147 /*
 148         //Set serial/modem config
 149         result=ipmi_request(6,serialmodem_conf);
 150         earlydbg(result);
 151
 152         //Set serial mux 1
 153         result=ipmi_request(4,serial_mux1);
 154         earlydbg(result);
 155
 156         //Set serial mux 2
 157         result=ipmi_request(4,serial_mux2);
 158         earlydbg(result);
 159
 160         //Set serial mux 3
 161         result=ipmi_request(4,serial_mux3);
 162         earlydbg(result);
 163 */
 164 //      earlydbg(0x0e);
 165
 166 }
 167 #endif
 168
 169 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 170 {
 171         static const uint16_t spd_addr[] = {
 172                 // first node
 173                  DIMM0, DIMM2, 0, 0,
 174                  DIMM1, DIMM3, 0, 0,
 175
 176                 // second node
 177                 DIMM4, DIMM6, 0, 0,
 178                 DIMM5, DIMM7, 0, 0,
 179         };
 180
 181         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 182                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 183
 184         int needs_reset;
 185         unsigned bsp_apicid = 0;
 186
 187         if (!cpu_init_detectedx && boot_cpu()) {
 188                 /* Nothing special needs to be done to find bus 0 */
 189                 /* Allow the HT devices to be found */
 190
 191                 enumerate_ht_chain();
 192                 bcm5785_enable_rom();
 193                 bcm5785_enable_lpc();
 194                 //enable RTC
 195                 pc87417_enable_dev(RTC_DEV);
 196         }
 197
 198         if (bist == 0) {
 199                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 200         }
 201
 202         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 203
 204         uart_init();
 205
 206         /* Halt if there was a built in self test failure */
 207         report_bist_failure(bist);
 208
 209         console_init();
 210 //      setup_early_ipmi_serial();
 211         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 212         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 213         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 214
 215 #if CONFIG_MEM_TRAIN_SEQ == 1
 216         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 217 #endif
 218         setup_coherent_ht_domain();
 219
 220         wait_all_core0_started();
 221 #if CONFIG_LOGICAL_CPUS==1
 222         // It is said that we should start core1 after all core0 launched
 223         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 224          * So here need to make sure last core0 is started, esp for two way system,
 225          * (there may be apic id conflicts in that case)
 226         */
 227         start_other_cores();
 228         wait_all_other_cores_started(bsp_apicid);
 229 #endif
 230
 231         /* it will set up chains and store link pair for optimization later */
 232         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 233         bcm5785_early_setup();
 234
 235 #if SET_FIDVID == 1
 236         {
 237                 msr_t msr;
 238                 msr=rdmsr(0xc0010042);
 239                 printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 240         }
 241         enable_fid_change();
 242         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 243         init_fidvid_bsp(bsp_apicid);
 244         // show final fid and vid
 245         {
 246                 msr_t msr;
 247                 msr=rdmsr(0xc0010042);
 248                 printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 249         }
 250 #endif
 251
 252         needs_reset = optimize_link_coherent_ht();
 253         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 254
 255         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 256         if (needs_reset) {
 257                 printk(BIOS_INFO, "ht reset -\n");
 258                 soft_reset();
 259         }
 260
 261         allow_all_aps_stop(bsp_apicid);
 262
 263         //It's the time to set ctrl in sysinfo now;
 264         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 265         enable_smbus();
 266
 267         //do we need apci timer, tsc...., only debug need it for better output
 268         /* all ap stopped? */
 269         // init_timer(); // Need to use TMICT to synconize FID/VID
 270
 271         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 272
 273         post_cache_as_ram();
 274 }
 275