src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #define ASSEMBLY 1
  29 #define __PRE_RAM__
  30
  31 #define RAMINIT_SYSINFO 1
  32
  33 #define K8_ALLOCATE_IO_RANGE 1
  34
  35 #define QRANK_DIMM_SUPPORT 1
  36
  37 #if CONFIG_LOGICAL_CPUS==1
  38 #define SET_NB_CFG_54 1
  39 #endif
  40
  41 //used by init_cpus and fidvid
  42 #define K8_SET_FIDVID 1
  43 //if we want to wait for core1 done before DQS training, set it to 0
  44 #define K8_SET_FIDVID_CORE0_ONLY 1
  45
  46 #if CONFIG_K8_REV_F_SUPPORT == 1
  47 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  48 #endif
  49
  50 #define DBGP_DEFAULT 7
  51
  52 #include <stdint.h>
  53 #include <string.h>
  54 #include <device/pci_def.h>
  55 #include <device/pci_ids.h>
  56 #include <arch/io.h>
  57 #include <device/pnp_def.h>
  58 #include <arch/romcc_io.h>
  59 #include <cpu/x86/lapic.h>
  60 #include "option_table.h"
  61 #include "pc80/mc146818rtc_early.c"
  62
  63
  64 #if CONFIG_USE_FAILOVER_IMAGE==0
  65 #include "pc80/serial.c"
  66 #include "arch/i386/lib/console.c"
  67 #include "lib/ramtest.c"
  68
  69 #include <cpu/amd/model_fxx_rev.h>
  70
  71 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  72 #include "northbridge/amd/amdk8/raminit.h"
  73 #include "cpu/amd/model_fxx/apic_timer.c"
  74 #include "lib/delay.c"
  75
  76 #endif
  77
  78 #include "cpu/x86/lapic/boot_cpu.c"
  79 #include "northbridge/amd/amdk8/reset_test.c"
  80
  81 #include "superio/serverengines/pilot/pilot_early_serial.c"
  82 #include "superio/serverengines/pilot/pilot_early_init.c"
  83 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  84
  85
  86 #if CONFIG_USE_FAILOVER_IMAGE==0
  87
  88 #include "cpu/x86/bist.h"
  89
  90 #include "northbridge/amd/amdk8/debug.c"
  91
  92 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  93
  94 #include "northbridge/amd/amdk8/setup_resource_map.c"
  95
  96 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  97 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  98
  99 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 100
 101 static void memreset_setup(void)
 102 {
 103 }
 104
 105 static void memreset(int controllers, const struct mem_controller *ctrl)
 106 {
 107 }
 108
 109 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 110 {
 111 #define SMBUS_SWITCH1 0x70
 112 #define SMBUS_SWITCH2 0x72
 113          unsigned device = (ctrl->channel0[0]) >> 8;
 114          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
 115          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
 116 }
 117
 118 static inline int spd_read_byte(unsigned device, unsigned address)
 119 {
 120          return smbus_read_byte(device, address);
 121 }
 122
 123 #include "northbridge/amd/amdk8/amdk8_f.h"
 124 #include "northbridge/amd/amdk8/coherent_ht.c"
 125
 126 #include "northbridge/amd/amdk8/incoherent_ht.c"
 127
 128 #include "northbridge/amd/amdk8/raminit_f.c"
 129
 130 #include "lib/generic_sdram.c"
 131
 132 //#include "resourcemap.c"
 133
 134 #include "cpu/amd/dualcore/dualcore.c"
 135
 136 //first node
 137 #define DIMM0 0x50
 138 #define DIMM1 0x51
 139 #define DIMM2 0x52
 140 #define DIMM3 0x53
 141 //second node
 142 #define DIMM4 0x54
 143 #define DIMM5 0x55
 144 #define DIMM6 0x56
 145 #define DIMM7 0x57
 146
 147
 148 #include "cpu/amd/car/copy_and_run.c"
 149
 150 #include "cpu/amd/car/post_cache_as_ram.c"
 151
 152 #include "cpu/amd/model_fxx/init_cpus.c"
 153
 154 #include "cpu/amd/model_fxx/fidvid.c"
 155
 156 #endif
 157
 158 #include "northbridge/amd/amdk8/early_ht.c"
 159
 160 #if 0
 161 #include "ipmi.c"
 162
 163 static void setup_early_ipmi_serial()
 164 {
 165         unsigned char result;
 166         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 167         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 168         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 169         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 170         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 171
 172 //      earlydbg(0x0d);
 173         //set channel access system only
 174         ipmi_request(5,channel_access);
 175 //      earlydbg(result);
 176 /*
 177         //Set serial/modem config
 178         result=ipmi_request(6,serialmodem_conf);
 179         earlydbg(result);
 180
 181         //Set serial mux 1
 182         result=ipmi_request(4,serial_mux1);
 183         earlydbg(result);
 184
 185         //Set serial mux 2
 186         result=ipmi_request(4,serial_mux2);
 187         earlydbg(result);
 188
 189         //Set serial mux 3
 190         result=ipmi_request(4,serial_mux3);
 191         earlydbg(result);
 192 */
 193 //      earlydbg(0x0e);
 194
 195 }
 196 #endif
 197
 198 #if CONFIG_USE_FAILOVER_IMAGE==0
 199
 200 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 201 {
 202         static const uint16_t spd_addr[] = {
 203                 //first node
 204                  DIMM0, DIMM2, 0, 0,
 205                  DIMM1, DIMM3, 0, 0,
 206 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 207                 //second node
 208                 DIMM4, DIMM6, 0, 0,
 209                 DIMM5, DIMM7, 0, 0,
 210 #endif
 211
 212         };
 213
 214         struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 215
 216          int needs_reset;
 217          unsigned bsp_apicid = 0;
 218
 219          if (!cpu_init_detectedx && boot_cpu()) {
 220                  /* Nothing special needs to be done to find bus 0 */
 221                  /* Allow the HT devices to be found */
 222
 223                  enumerate_ht_chain();
 224                  bcm5785_enable_rom();
 225                  bcm5785_enable_lpc();
 226                  //enable RTC
 227                 pc87417_enable_dev(RTC_DEV);
 228          }
 229
 230
 231          if (bist == 0) {
 232                  bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 233          }
 234
 235         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 236
 237         //setup_mp_resource_map();
 238
 239         uart_init();
 240
 241         /* Halt if there was a built in self test failure */
 242         report_bist_failure(bist);
 243
 244
 245         console_init();
 246 //      setup_early_ipmi_serial();
 247         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 248         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 249
 250         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 251
 252 #if CONFIG_MEM_TRAIN_SEQ == 1
 253         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 254 #endif
 255         setup_coherent_ht_domain();
 256
 257         wait_all_core0_started();
 258 #if CONFIG_LOGICAL_CPUS==1
 259         // It is said that we should start core1 after all core0 launched
 260         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 261          * So here need to make sure last core0 is started, esp for two way system,
 262          * (there may be apic id conflicts in that case)
 263         */
 264         start_other_cores();
 265         wait_all_other_cores_started(bsp_apicid);
 266 #endif
 267
 268         /* it will set up chains and store link pair for optimization later */
 269         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 270         bcm5785_early_setup();
 271
 272 #if K8_SET_FIDVID == 1
 273         {
 274                 msr_t msr;
 275                 msr=rdmsr(0xc0010042);
 276                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 277         }
 278         enable_fid_change();
 279         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 280         init_fidvid_bsp(bsp_apicid);
 281         // show final fid and vid
 282         {
 283                 msr_t msr;
 284                 msr=rdmsr(0xc0010042);
 285                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 286         }
 287 #endif
 288
 289         needs_reset = optimize_link_coherent_ht();
 290         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 291
 292         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 293         if (needs_reset) {
 294                 print_info("ht reset -\r\n");
 295                 soft_reset();
 296         }
 297
 298         allow_all_aps_stop(bsp_apicid);
 299
 300         //It's the time to set ctrl in sysinfo now;
 301         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 302         enable_smbus();
 303
 304         memreset_setup();
 305         //do we need apci timer, tsc...., only debug need it for better output
 306         /* all ap stopped? */
 307 //      init_timer(); // Need to use TMICT to synconize FID/VID
 308
 309         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 310
 311         post_cache_as_ram();
 312
 313 }
 314
 315 #endif