src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #define K8_ALLOCATE_IO_RANGE 1
  29
  30 #define QRANK_DIMM_SUPPORT 1
  31
  32 #if CONFIG_LOGICAL_CPUS==1
  33 #define SET_NB_CFG_54 1
  34 #endif
  35
  36 //used by init_cpus and fidvid
  37 #define SET_FIDVID 1
  38 //if we want to wait for core1 done before DQS training, set it to 0
  39 #define SET_FIDVID_CORE0_ONLY 1
  40
  41 #if CONFIG_K8_REV_F_SUPPORT == 1
  42 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  43 #endif
  44
  45 #include <stdint.h>
  46 #include <string.h>
  47 #include <device/pci_def.h>
  48 #include <device/pci_ids.h>
  49 #include <arch/io.h>
  50 #include <device/pnp_def.h>
  51 #include <arch/romcc_io.h>
  52 #include <cpu/x86/lapic.h>
  53 #include <pc80/mc146818rtc.h>
  54
  55 #include <console/console.h>
  56
  57 #include <cpu/amd/model_fxx_rev.h>
  58
  59 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  60 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  61 #include "northbridge/amd/amdk8/raminit.h"
  62 #include "cpu/amd/model_fxx/apic_timer.c"
  63 #include "lib/delay.c"
  64
  65 #include "cpu/x86/lapic/boot_cpu.c"
  66 #include "northbridge/amd/amdk8/reset_test.c"
  67
  68 #include "superio/serverengines/pilot/pilot_early_serial.c"
  69 #include "superio/serverengines/pilot/pilot_early_init.c"
  70 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  71
  72 #include "cpu/x86/bist.h"
  73
  74 #include "northbridge/amd/amdk8/debug.c"
  75
  76 #include "cpu/x86/mtrr/earlymtrr.c"
  77
  78 #include "northbridge/amd/amdk8/setup_resource_map.c"
  79
  80 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  81 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  82
  83 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  84
  85 static void memreset(int controllers, const struct mem_controller *ctrl)
  86 {
  87 }
  88
  89 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  90 {
  91 #define SMBUS_SWITCH1 0x70
  92 #define SMBUS_SWITCH2 0x72
  93          unsigned device = (ctrl->channel0[0]) >> 8;
  94          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  95          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  96 }
  97
  98 static inline int spd_read_byte(unsigned device, unsigned address)
  99 {
 100          return smbus_read_byte(device, address);
 101 }
 102
 103 #include "northbridge/amd/amdk8/amdk8_f.h"
 104 #include "northbridge/amd/amdk8/incoherent_ht.c"
 105 #include "northbridge/amd/amdk8/coherent_ht.c"
 106 #include "northbridge/amd/amdk8/raminit_f.c"
 107 #include "lib/generic_sdram.c"
 108
 109 #include "cpu/amd/dualcore/dualcore.c"
 110
 111 //first node
 112 #define DIMM0 0x50
 113 #define DIMM1 0x51
 114 #define DIMM2 0x52
 115 #define DIMM3 0x53
 116 //second node
 117 #define DIMM4 0x54
 118 #define DIMM5 0x55
 119 #define DIMM6 0x56
 120 #define DIMM7 0x57
 121
 122
 123
 124 #include "cpu/amd/car/post_cache_as_ram.c"
 125
 126 #include "cpu/amd/model_fxx/init_cpus.c"
 127
 128 #include "cpu/amd/model_fxx/fidvid.c"
 129
 130 #include "northbridge/amd/amdk8/early_ht.c"
 131
 132 #if 0
 133 #include "ipmi.c"
 134
 135 static void setup_early_ipmi_serial()
 136 {
 137         unsigned char result;
 138         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 139         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 140         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 141         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 142         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 143
 144 //      earlydbg(0x0d);
 145         //set channel access system only
 146         ipmi_request(5,channel_access);
 147 //      earlydbg(result);
 148 /*
 149         //Set serial/modem config
 150         result=ipmi_request(6,serialmodem_conf);
 151         earlydbg(result);
 152
 153         //Set serial mux 1
 154         result=ipmi_request(4,serial_mux1);
 155         earlydbg(result);
 156
 157         //Set serial mux 2
 158         result=ipmi_request(4,serial_mux2);
 159         earlydbg(result);
 160
 161         //Set serial mux 3
 162         result=ipmi_request(4,serial_mux3);
 163         earlydbg(result);
 164 */
 165 //      earlydbg(0x0e);
 166
 167 }
 168 #endif
 169
 170 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 171 {
 172         static const uint16_t spd_addr[] = {
 173                 // first node
 174                  DIMM0, DIMM2, 0, 0,
 175                  DIMM1, DIMM3, 0, 0,
 176
 177                 // second node
 178                 DIMM4, DIMM6, 0, 0,
 179                 DIMM5, DIMM7, 0, 0,
 180         };
 181
 182         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 183                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 184
 185         int needs_reset;
 186         unsigned bsp_apicid = 0;
 187
 188         if (!cpu_init_detectedx && boot_cpu()) {
 189                 /* Nothing special needs to be done to find bus 0 */
 190                 /* Allow the HT devices to be found */
 191
 192                 enumerate_ht_chain();
 193                 bcm5785_enable_rom();
 194                 bcm5785_enable_lpc();
 195                 //enable RTC
 196                 pc87417_enable_dev(RTC_DEV);
 197         }
 198
 199         if (bist == 0) {
 200                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 201         }
 202
 203         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 204
 205         uart_init();
 206
 207         /* Halt if there was a built in self test failure */
 208         report_bist_failure(bist);
 209
 210         console_init();
 211 //      setup_early_ipmi_serial();
 212         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 213         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 214         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 215
 216 #if CONFIG_MEM_TRAIN_SEQ == 1
 217         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 218 #endif
 219         setup_coherent_ht_domain();
 220
 221         wait_all_core0_started();
 222 #if CONFIG_LOGICAL_CPUS==1
 223         // It is said that we should start core1 after all core0 launched
 224         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 225          * So here need to make sure last core0 is started, esp for two way system,
 226          * (there may be apic id conflicts in that case)
 227         */
 228         start_other_cores();
 229         wait_all_other_cores_started(bsp_apicid);
 230 #endif
 231
 232         /* it will set up chains and store link pair for optimization later */
 233         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 234         bcm5785_early_setup();
 235
 236 #if SET_FIDVID == 1
 237         {
 238                 msr_t msr;
 239                 msr=rdmsr(0xc0010042);
 240                 printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 241         }
 242         enable_fid_change();
 243         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 244         init_fidvid_bsp(bsp_apicid);
 245         // show final fid and vid
 246         {
 247                 msr_t msr;
 248                 msr=rdmsr(0xc0010042);
 249                 printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 250         }
 251 #endif
 252
 253         needs_reset = optimize_link_coherent_ht();
 254         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 255
 256         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 257         if (needs_reset) {
 258                 printk(BIOS_INFO, "ht reset -\n");
 259                 soft_reset();
 260         }
 261
 262         allow_all_aps_stop(bsp_apicid);
 263
 264         //It's the time to set ctrl in sysinfo now;
 265         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 266         enable_smbus();
 267
 268         //do we need apci timer, tsc...., only debug need it for better output
 269         /* all ap stopped? */
 270         // init_timer(); // Need to use TMICT to synconize FID/VID
 271
 272         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 273
 274         post_cache_as_ram();
 275 }
 276