src/mainboard/hp/dl145_g3/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2007 University of Mannheim
  10  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
  11  *
  12  * Copyright (C) 2009 University of Heidelberg
  13  * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  28  */
  29
  30 #include <console/console.h>
  31 #include <arch/smp/mpspec.h>
  32 #include <arch/io.h>
  33 #include <device/pci.h>
  34 #include <string.h>
  35 #include <stdint.h>
  36 #if CONFIG_LOGICAL_CPUS==1
  37 #include <cpu/amd/multicore.h>
  38 #endif
  39
  40 #include <cpu/amd/amdk8_sysconf.h>
  41
  42 #include "mb_sysconf.h"
  43
  44
  45
  46 static void *smp_write_config_table(void *v)
  47 {
  48         static const char sig[4] = "PCMP";
  49         static const char oem[8] = "COREBOOT";
  50         static const char productid[12] = "TREX        ";
  51         struct mp_config_table *mc;
  52
  53         struct mb_sysconf_t *m;
  54
  55         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  56         memset(mc, 0, sizeof(*mc));
  57
  58         memcpy(mc->mpc_signature, sig, sizeof(sig));
  59         mc->mpc_length = sizeof(*mc); /* initially just the header */
  60         mc->mpc_spec = 0x04;
  61         mc->mpc_checksum = 0; /* not yet computed */
  62         memcpy(mc->mpc_oem, oem, sizeof(oem));
  63         memcpy(mc->mpc_productid, productid, sizeof(productid));
  64         mc->mpc_oemptr = 0;
  65         mc->mpc_oemsize = 0;
  66         mc->mpc_entry_count = 0; /* No entries yet... */
  67         mc->mpc_lapic = LAPIC_ADDR;
  68         mc->mpe_length = 0;
  69         mc->mpe_checksum = 0;
  70         mc->reserved = 0;
  71
  72         smp_write_processors(mc);
  73
  74         get_bus_conf();
  75         m = sysconf.mb;
  76
  77         /*Bus:         Bus ID  Type*/
  78         /* define bus and isa numbers */
  79 #if 0
  80         unsigned char bus_num;
  81         for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
  82                 smp_write_bus(mc, bus_num, "PCI   ");
  83                 printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num);
  84         }
  85 #endif
  86         smp_write_bus(mc, 0, "PCI   ");
  87         smp_write_bus(mc, 1, "PCI   ");
  88         smp_write_bus(mc, 7, "PCI   ");
  89         smp_write_bus(mc, 8, "PCI   ");
  90
  91         smp_write_bus(mc,m->bus_isa, "ISA   ");
  92         printk(BIOS_DEBUG, "writing %d as ISA...\n",m->bus_isa);
  93
  94         /*I/O APICs:   APIC ID Version State           Address*/
  95         {
  96                 device_t dev = 0;
  97                 int i;
  98                 struct resource *res;
  99                 for(i=0; i<3; i++) {
 100                         dev = dev_find_device(0x1166, 0x0235, dev);
 101                         if (dev) {
 102                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 103                                 if (res) {
 104                                         printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i],  res->base);
 105                                         smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
 106                                 }
 107                         }
 108                 }
 109
 110         }
 111
 112         /* IRQ routing as factory BIOS */
 113         outb(0x01, 0xc00); outb(0x0A, 0xc01);
 114         outb(0x17, 0xc00); outb(0x05, 0xc01);
 115 /*      outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
 116 /*      outb(0x07, 0xc00); outb(0x07, 0xc01); */
 117         outb(0x07, 0xc00); outb(0x0b, 0xc01);
 118
 119         outb(0x24, 0xc00); outb(0x05, 0xc01);
 120         //outb(0x00, 0xc00); outb(0x09, 0xc01);
 121         outb(0x02, 0xc00); outb(0x0E, 0xc01);
 122
 123         // 8259 registers...
 124         outb(0xa0, 0x4d0);
 125         outb(0x0e, 0x4d1);
 126
 127         {
 128                 device_t dev;
 129                 dev = dev_find_device(0x1166, 0x0205, 0);
 130                 if(dev) {
 131                         uint32_t dword;
 132                         dword = pci_read_config32(dev, 0x64);
 133                         dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
 134                         pci_write_config32(dev, 0x64, dword);
 135                 }
 136                 // set GEVENT pins to NO OP
 137                 outb(0x33, 0xcd6); outb(0x00, 0xcd7);
 138                 outb(0x34, 0xcd6); outb(0x00, 0xcd7);
 139                 outb(0x35, 0xcd6); outb(0x00, 0xcd7);
 140         }
 141
 142         // hide XIOAPIC PCI configuration space
 143         {
 144                 device_t dev;
 145                 dev = dev_find_device(0x1166, 0x205, 0);
 146                 if (dev) {
 147                         uint32_t dword;
 148                         dword = pci_read_config32(dev, 0x64);
 149                         dword |= (1<<26);
 150                         pci_write_config32(dev, 0x64, dword);
 151                 }
 152         }
 153
 154         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0);
 155
 156         //SATA
 157 /*      printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 158 /*      smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 159         printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 160         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 161         //USB
 162         printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
 163         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
 164
 165         //VGA
 166         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
 167
 168         //PCIE
 169         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
 170         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
 171         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
 172         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
 173         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
 174
 175         //IDE
 176 //      outb(0x02, 0xc00); outb(0x0e, 0xc01);
 177 //      printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
 178 //              smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
 179
 180         //onboard Broadcom GbE
 181         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
 182         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
 183
 184
 185
 186         /* enable int */
 187         /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
 188         {
 189                 device_t dev;
 190                 dev = dev_find_device(0x1166, 0x0205, 0);
 191                 if(dev) {
 192                         uint32_t dword;
 193                         dword = pci_read_config32(dev, 0x6c);
 194                         dword |= (1<<4); // enable interrupts
 195                         printk(BIOS_DEBUG, "6ch: %x\n",dword);
 196                         pci_write_config32(dev, 0x6c, dword);
 197                 }
 198         }
 199
 200 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 201         printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa);
 202         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 203         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1);
 204
 205         //extended table entries
 206         smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
 207         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
 208         smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
 209         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
 210         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
 211         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
 212         smp_write_bus_hierarchy(mc, 9, 0x01, 0);
 213         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
 214         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
 215
 216
 217         /* Compute the checksums */
 218         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 219         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 220         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 221                 mc, smp_next_mpe_entry(mc));
 222         return smp_next_mpe_entry(mc);
 223 }
 224
 225 unsigned long write_smp_table(unsigned long addr)
 226 {
 227         void *v;
 228         v = smp_write_floating_table(addr);
 229         return (unsigned long)smp_write_config_table(v);
 230 }