2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2007 University of Mannheim
8 ## Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
10 ## Copyright (C) 2009 University of Heidelberg
11 ## Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
13 ## This program is free software; you can redistribute it and/or modify
14 ## it under the terms of the GNU General Public License as published by
15 ## the Free Software Foundation; either version 2 of the License, or
16 ## (at your option) any later version.
18 ## This program is distributed in the hope that it will be useful,
19 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
20 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 ## GNU General Public License for more details.
23 ## You should have received a copy of the GNU General Public License
24 ## along with this program; if not, write to the Free Software
25 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
29 default CONFIG_XIP_ROM_SIZE = 64 * 1024
30 include /config/nofailovercalculation.lb
35 ## Build the objects we have code for in this directory.
40 #needed by irq_tables and mptable and acpi_tables
43 if CONFIG_GENERATE_MP_TABLE object mptable.o end
44 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
48 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
49 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
53 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
54 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
55 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
56 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
61 ## Build our 16 bit and 32 bit coreboot entry code
63 if CONFIG_USE_FALLBACK_IMAGE
64 mainboardinit cpu/x86/16bit/entry16.inc
65 ldscript /cpu/x86/16bit/entry16.lds
68 mainboardinit cpu/x86/32bit/entry32.inc
71 ldscript /cpu/x86/32bit/entry32.lds
75 ldscript /cpu/amd/car/cache_as_ram.lds
79 ## Build our reset vector (This is where coreboot is entered)
81 if CONFIG_USE_FALLBACK_IMAGE
82 mainboardinit cpu/x86/16bit/reset16.inc
83 ldscript /cpu/x86/16bit/reset16.lds
85 mainboardinit cpu/x86/32bit/reset32.inc
86 ldscript /cpu/x86/32bit/reset32.lds
90 ## Include an id string (For safe flashing)
92 mainboardinit arch/i386/lib/id.inc
93 ldscript /arch/i386/lib/id.lds
98 mainboardinit cpu/amd/car/cache_as_ram.inc
101 ### This is the early phase of coreboot startup
102 ### Things are delicate and we test to see if we should
103 ### failover to another image.
105 if CONFIG_USE_FALLBACK_IMAGE
106 ldscript /arch/i386/lib/failover.lds
110 ### O.k. We aren't just an intermediary anymore!
119 mainboardinit ./auto.inc
123 # config for hp/dl145_g3
124 chip northbridge/amd/amdk8/root_complex
125 device apic_cluster 0 on
126 chip cpu/amd/socket_F
130 device pci_domain 0 on
131 chip northbridge/amd/amdk8 # northbridge
132 device pci 18.0 on # devices on link 0
133 chip southbridge/broadcom/bcm21000 # HT2100
135 end # bridge to slot PCI-E 4x ??
140 device pci 3.0 on # bridge to slot PCI-E 16x ??
145 device pci 4.0 on end # BCM5715 NIC
146 device pci 4.1 on end # BCM5715 NIC
149 chip southbridge/broadcom/bcm5785 # HT1000
150 device pci 0.0 on # HT PXB 0x0036
151 device pci d.0 on end # PCI/PCI-X bridge 0x0104
152 device pci e.0 on end # SATA 0x024a
154 device pci 1.0 on end # Legacy pci main 0x0205
155 device pci 1.1 on end # IDE 0x0214
156 device pci 1.2 on # LPC 0x0234
157 chip superio/nsc/pc87417
158 device pnp 4e.0 off # Floppy
163 device pnp 4e.1 off # Parallel Port
167 device pnp 4e.2 off # Com 2
171 device pnp 4e.3 off # Com 1
175 device pnp 4e.4 off end # SWC
176 device pnp 4e.5 off end # Mouse
177 device pnp 4e.6 off # Keyboard
182 device pnp 4e.7 off end # GPIO
183 device pnp 4e.f off end # XBUS
184 device pnp 4e.10 on #RTC
190 device pci 1.3 off end # WDTimer 0x0238
191 device pci 1.4 on end # XIOAPIC0 0x0235
192 device pci 1.5 on end # XIOAPIC1
193 device pci 1.6 on end # XIOAPIC2
194 device pci 2.0 on end # USB 0x0223
195 device pci 2.1 on end # USB
196 device pci 2.2 on end # USB
197 device pci 3.0 on end # VGA
200 #chip drivers/pci/onboard #SATA2
201 # device pci 5.0 on end
202 # device pci 5.1 on end
203 # device pci 5.2 on end
204 # device pci 5.3 on end
209 device pci 18.0 on end
210 device pci 18.0 on end
211 device pci 18.1 on end
212 device pci 18.2 on end
213 device pci 18.3 on end