2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2007 University of Mannheim
8 ## Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
10 ## Copyright (C) 2009 University of Heidelberg
11 ## Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
13 ## This program is free software; you can redistribute it and/or modify
14 ## it under the terms of the GNU General Public License as published by
15 ## the Free Software Foundation; either version 2 of the License, or
16 ## (at your option) any later version.
18 ## This program is distributed in the hope that it will be useful,
19 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
20 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 ## GNU General Public License for more details.
23 ## You should have received a copy of the GNU General Public License
24 ## along with this program; if not, write to the Free Software
25 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 include /config/nofailovercalculation.lb
33 ## Build the objects we have code for in this directory.
38 #needed by irq_tables and mptable and acpi_tables
41 if HAVE_MP_TABLE object mptable.o end
42 if HAVE_PIRQ_TABLE object irq_tables.o end
46 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
47 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
51 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
52 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
53 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
54 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
59 ## Build our 16 bit and 32 bit coreboot entry code
62 mainboardinit cpu/x86/16bit/entry16.inc
63 ldscript /cpu/x86/16bit/entry16.lds
66 mainboardinit cpu/x86/32bit/entry32.inc
69 ldscript /cpu/x86/32bit/entry32.lds
73 ldscript /cpu/amd/car/cache_as_ram.lds
77 ## Build our reset vector (This is where coreboot is entered)
80 mainboardinit cpu/x86/16bit/reset16.inc
81 ldscript /cpu/x86/16bit/reset16.lds
83 mainboardinit cpu/x86/32bit/reset32.inc
84 ldscript /cpu/x86/32bit/reset32.lds
88 ## Include an id string (For safe flashing)
90 mainboardinit arch/i386/lib/id.inc
91 ldscript /arch/i386/lib/id.lds
96 mainboardinit cpu/amd/car/cache_as_ram.inc
99 ### This is the early phase of coreboot startup
100 ### Things are delicate and we test to see if we should
101 ### failover to another image.
103 if USE_FALLBACK_IMAGE
104 ldscript /arch/i386/lib/failover.lds
108 ### O.k. We aren't just an intermediary anymore!
117 mainboardinit ./auto.inc
121 # config for hp/dl145_g3
122 chip northbridge/amd/amdk8/root_complex
123 device apic_cluster 0 on
124 chip cpu/amd/socket_F
128 device pci_domain 0 on
129 chip northbridge/amd/amdk8 # northbridge
130 device pci 18.0 on # devices on link 0
131 chip southbridge/broadcom/bcm21000 # HT2100
133 end # bridge to slot PCI-E 4x ??
138 device pci 3.0 on # bridge to slot PCI-E 16x ??
143 device pci 4.0 on end # BCM5715 NIC
144 device pci 4.1 on end # BCM5715 NIC
147 chip southbridge/broadcom/bcm5785 # HT1000
148 device pci 0.0 on # HT PXB 0x0036
149 device pci d.0 on end # PCI/PCI-X bridge 0x0104
150 device pci e.0 on end # SATA 0x024a
152 device pci 1.0 on end # Legacy pci main 0x0205
153 device pci 1.1 on end # IDE 0x0214
154 device pci 1.2 on # LPC 0x0234
155 chip superio/nsc/pc87417
156 device pnp 4e.0 off # Floppy
161 device pnp 4e.1 off # Parallel Port
165 device pnp 4e.2 off # Com 2
169 device pnp 4e.3 off # Com 1
173 device pnp 4e.4 off end # SWC
174 device pnp 4e.5 off end # Mouse
175 device pnp 4e.6 off # Keyboard
180 device pnp 4e.7 off end # GPIO
181 device pnp 4e.f off end # XBUS
182 device pnp 4e.10 on #RTC
188 device pci 1.3 off end # WDTimer 0x0238
189 device pci 1.4 on end # XIOAPIC0 0x0235
190 device pci 1.5 on end # XIOAPIC1
191 device pci 1.6 on end # XIOAPIC2
192 device pci 2.0 on end # USB 0x0223
193 device pci 2.1 on end # USB
194 device pci 2.2 on end # USB
195 device pci 3.0 on end # VGA
198 #chip drivers/pci/onboard #SATA2
199 # device pci 5.0 on end
200 # device pci 5.1 on end
201 # device pci 5.2 on end
202 # device pci 5.3 on end
207 device pci 18.0 on end
208 device pci 18.0 on end
209 device pci 18.1 on end
210 device pci 18.2 on end
211 device pci 18.3 on end