src/mainboard/hp/dl145_g1/romstage.c

   1
   2 #if CONFIG_LOGICAL_CPUS==1
   3 #define SET_NB_CFG_54 1
   4 #endif
   5
   6 #include <stdint.h>
   7 #include <string.h>
   8 #include <device/pci_def.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  28
  29 #include "cpu/x86/mtrr/earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #include "northbridge/amd/amdk8/setup_resource_map.c"
  33
  34 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  35
  36 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  37
  38 static void memreset_setup(void)
  39 {
  40    if (is_cpu_pre_c0()) {
  41       /* Set the memreset low */
  42       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  43       /* Ensure the BIOS has control of the memory lines */
  44       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  45    } else {
  46       /* Ensure the CPU has controll of the memory lines */
  47       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  48    }
  49 }
  50
  51 static void memreset(int controllers, const struct mem_controller *ctrl)
  52 {
  53    if (is_cpu_pre_c0()) {
  54       udelay(800);
  55       /* Set memreset_high */
  56       outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  57       udelay(90);
  58    }
  59 }
  60
  61 #define SMBUS_HUB 0x18
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65   int ret,i;
  66   unsigned device=(ctrl->channel0[0])>>8;
  67   /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  68   i=2;
  69   do {
  70     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  71   } while ((ret!=0) && (i-->0));
  72
  73   smbus_write_byte(SMBUS_HUB, 0x03, 0);
  74 }
  75
  76 static inline void change_i2c_mux(unsigned device)
  77 {
  78   int ret, i;
  79   print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  80   i=2;
  81   do {
  82     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  83     print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  84   } while ((ret!=0) && (i-->0));
  85   ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  86   print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  87 }
  88
  89 static inline int spd_read_byte(unsigned device, unsigned address)
  90 {
  91         return smbus_read_byte(device, address);
  92 }
  93
  94 #include "northbridge/amd/amdk8/raminit.c"
  95 #include "resourcemap.c"
  96 #include "northbridge/amd/amdk8/coherent_ht.c"
  97 #include "lib/generic_sdram.c"
  98
  99 #include "cpu/amd/dualcore/dualcore.c"
 100
 101 #define RC0 ((1<<1)<<8) // Not sure about these values
 102 #define RC1 ((1<<2)<<8) // Not sure about these values
 103
 104 #define DIMM0 0x50
 105 #define DIMM1 0x51
 106 #define DIMM2 0x52
 107 #define DIMM3 0x53
 108
 109 #include "cpu/amd/car/post_cache_as_ram.c"
 110
 111 #include "cpu/amd/model_fxx/init_cpus.c"
 112
 113 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 114 #include "northbridge/amd/amdk8/early_ht.c"
 115
 116
 117 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 118 {
 119         static const uint16_t spd_addr [] = {
 120                         //first node
 121                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 122                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 123 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 124                         //second node
 125                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 126                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 127 #endif
 128         };
 129
 130         int needs_reset;
 131         unsigned bsp_apicid = 0;
 132
 133         struct mem_controller ctrl[8];
 134         unsigned nodes;
 135
 136         if (!cpu_init_detectedx && boot_cpu()) {
 137                 /* Nothing special needs to be done to find bus 0 */
 138                 /* Allow the HT devices to be found */
 139
 140                 enumerate_ht_chain();
 141
 142                 /* Setup the amd8111 */
 143                 amd8111_enable_rom();
 144         }
 145
 146         if (bist == 0) {
 147                 bsp_apicid = init_cpus(cpu_init_detectedx);
 148         }
 149
 150 //      post_code(0x32);
 151
 152         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 153         uart_init();
 154         console_init();
 155
 156         /* Halt if there was a built in self test failure */
 157         report_bist_failure(bist);
 158
 159         setup_dl145g1_resource_map();
 160         //setup_default_resource_map();
 161
 162         needs_reset = setup_coherent_ht_domain();
 163
 164         wait_all_core0_started();
 165 #if CONFIG_LOGICAL_CPUS==1
 166         // It is said that we should start core1 after all core0 launched
 167         start_other_cores();
 168         wait_all_other_cores_started(bsp_apicid);
 169 #endif
 170
 171         needs_reset |= ht_setup_chains_x();
 172
 173         if (needs_reset) {
 174                 print_info("ht reset -\n");
 175                 soft_reset();
 176         }
 177
 178         enable_smbus();
 179
 180         int i;
 181         for(i=0;i<2;i++) {
 182                 activate_spd_rom(&ctrl[i]);
 183         }
 184         for(i=2;i<8;i<<=1) {
 185                 change_i2c_mux(i);
 186         }
 187
 188         //dump_spd_registers(&ctrl[0]);
 189         //dump_spd_registers(&ctrl[1]);
 190         //dump_smbus_registers();
 191
 192         allow_all_aps_stop(bsp_apicid);
 193
 194         nodes = get_nodes();
 195         //It's the time to set ctrl now;
 196         fill_mem_ctrl(nodes, ctrl, spd_addr);
 197
 198         memreset_setup();
 199         sdram_initialize(nodes, ctrl);
 200
 201         //dump_pci_devices();
 202
 203         post_cache_as_ram();
 204 }